Signoff and Design Methodology Engineer, Silicon

Role Overview: As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. Key Responsibilities: - Drive sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. - Analyze power performance area trade-offs across various methodologies and technologies. - Work on prototyping subsystems to deliver optimized PPA recipes. - Collaborate with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology. - Engage with foundry partners to enhance signoff methodology for improved convergence and yield. Qualifications Required: - Bachelor's degree in Computer Science, IT, or related field, or equivalent practical experience. - Minimum 5 years of experience in static timing analysis, synthesis, physical design, and automation. - Expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. - Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog. - Strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies.,