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Signoff and Design Methodology Engineer, Silicon

Signoff and Design Methodology Engineer, Silicon

Google

5 - 10 years

30 - 35 Lacs

Bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

Automation Data analysis static timing analysis Architecture Verilog Silicon Hardware IPS Physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Minimum qualifications:

Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience.
5 years of experience with static timing analysis, synthesis, physical design & automation.
Experience in physical design tool automation such as synthesis, P&R and sign-off tools.

Preferred qualifications:

Experience in extraction of design parameters, Quality of Results metrics, and analyzing data trends.
Knowledge of timing constraints, convergence and signoff.
Knowledge of parasitic extraction tools and flow.
Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog).
Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Drive the sign-off timing methodologies for mobile System on a chip (SoCs) to push Power Performance Area (PPA) and yield.
Analyze power performance area trade-offs across different methodologies and technologies.
Work on prototyping of subsystems to deliver optimized PPA recipes.
Work with cross-functional architecture, Internet Protocols (IPs), design, power and sign-off methodology teams.
Work with foundry to refine signoff methodology to improve convergence and yield.

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Signoff and Design Methodology Engineer, Silicon