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Static Timing Methodology Development For Gate Level Timing Sign off

Static Timing Methodology Development For Gate Level Timing Sign off

IBM

3 - 8 years

8 - 11 Lacs

Bengaluru

Posted:3 hours ago| Platform:

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Skills Required

python static timing analysis semiconductor machine learning vlsi physical design communication engineering vhdl verilog artificial intelligence cadence strong interpersonal skills data science computer architecture shell scripting tcl

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering & Electronics & Communication Engineering ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Machine Learning/AI and/or Data Science background to lead our leading-edge algorithms and AI technology within our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise

Individual contributor for Gate Leve Sign off Timing team to work on ASICs or Server Timing Methodology.

3+ years of Semiconductor/VLSI experience

Proven problem-solving skills and the ability to work in a team environment are a must

EDA Tool/Methodology development experience

Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus

Excellent scripting skills - TCL/Python/Shell

Preferred technical and professional experience Cadence tools, Synopsys tools, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI

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Static Timing Methodology Development For Gate Level Timing Sign off