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Qualcomm
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Physical Design Engineer, Sr. / Lead / Staff

Physical Design Engineer, Sr. / Lead / Staff

Qualcomm

4 - 9 years

17 - 22 Lacs

hyderabad

Posted:2 hours ago| Platform:

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Skills Required

debugging scripting languages cts asic design pnr physical design c++ hiring android floorplan staffing routing java git drc html perl tcl sta python primetime hardware engineering lvs timing analysis javascript floor planning timing closure

Work Mode

Work from Office

Job Type

Full Time

Job Description

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PD JD:

Thorough knowledge of the ASIC designs Place and Route flow and methodology.
Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
Strong background in debugging Congestion and CTS issues.
Expertise in PnR tools (Innovus/Fusion compiler) and flow.
Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
Understand and implement improving existing methodologies and flows.
Proficient in scripting languages (TCL,PERL,PYTHON).
Self-starter and highly motivated
To have working experience in global team environment.
To be effectively communicate the status and issues of respective owned Tasks
4-10 yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

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Physical Design Engineer, Sr. / Lead / Staff