Job
Description
As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus. It is crucial to have a strong grasp of clocking architecture and work closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design. Proficiency in Tcl/Perl scripting, strong problem-solving skills, and effective communication skills are also required for this role. Key Responsibilities: - Perform physical implementation activities for sub-systems, including floor-planning, place and route, CTS, formal verification, physical verification, PDN, timing closure, and power optimization - Make appropriate PPA trade-off decisions for critical cores - Ensure timing convergence of high-frequency data-path intensive cores - Collaborate with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design - Utilize Tcl/Perl scripting for efficient workflow - Demonstrate strong problem-solving skills and effective communication abilities Qualifications Required: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field - 1-3 years of experience in Physical Design/Implementation Please note that Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require any assistance, you may contact disability-accommodations@qualcomm.com. Qualcomm also expects its employees to comply with all applicable policies and procedures, including those related to the protection of company confidential information. If you have any questions about this role, please reach out to Qualcomm Careers. As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus. It is crucial to have a strong grasp of clocking architecture and work closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design. Proficiency in Tcl/Perl scripting, strong problem-solving skills, and effective communication skills are also required for this role. Key Responsibilities: - Perform physical implementation activities for sub-systems, including floor-planning, place and route, CTS, formal verification, physical verification, PDN, timing closure, and power optimization - Make appropriate PPA trade-off decisions for critical cores - Ensure timing convergence of high-frequency data-path intensive cores - Collaborate with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design - Utilize Tcl/Perl scripting for efficient workflow - Demonstrate strong problem-solving skills and effective communication abilities Qualifications Required: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field - 1-3 years of experience in Physical Design/Implementation
