6 Clocking Architecture Jobs

As a Hardware Engineer at Qualcomm India Private Limited, your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Perform Physical Implementation activities for high-performance Cores for various technologies such as 16/14/7/5nm or lower - Tasks may include floor-planning, place and route, clock tree synthesis, for...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cade...

Join a dynamic team at Google working on custom silicon solutions for direct-to-consumer products. Your contributions will play a crucial role in shaping the future of hardware experiences, focusing on performance, efficiency, and integration. As a member of the Power team, you will be involved in cutting-edge power estimation techniques and collaborate with various teams to incorporate system requirements into power estimation methodologies. - Drive pre-silicon power estimation and analysis using power estimation tools at both Register-Transfer Level (RTL) and Netlist level. - Develop methodologies around power estimation tools and implement best practices to enhance power estimation accura...

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...