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Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. The role involves Physical Implementation activities for high-performance Cores for various technologies, including floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure, power optimization, and more. The ideal candidate should have exposure to PD implementation of PPA critical cores, timing convergence of high-frequency data-path intensive Cores, advanced STA concepts, clocking architecture, and should be proficient in Tcl/Python/Perl Scripting for automation. Strong problem-solving skills, communication skills, and the ability to work well in a team are essential. Collaboration with design, DFT, and PNR teams to support issue resolutions is also a key aspect of the role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Recruitment agencies are advised that Qualcomm's Careers Site is intended for individuals seeking jobs at Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required for this role. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. Proficiency in Tcl/Perl Scripting and strong problem-solving skills, along with effective communication skills, are vital for this position. Qualcomm India Private Limited is seeking candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in a relevant field and 1+ year of Hardware Engineering experience, or a PhD in a related field, are also acceptable qualifications. The ideal candidate should have 1-3 years of experience in Physical Design/Implementation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to security and the protection of Company and proprietary information. It is essential to ensure workplace accessibility for individuals with disabilities. For further information about this role, please contact Qualcomm Careers.,

You will be responsible for designing Material Handling Equipment, preparing Bill of Materials, creating models, collecting quotations for standard parts, drafting materials, and coordinating projects with production and other departments. To excel in this role, you should have experience in designing Roller Conveyors, Belt Conveyors, Gantry Systems, Special Purpose Machines, Turn Tables, Turnover Devices, Pick and Place systems, and possess proficiency in SolidWorks software. Additionally, you must have excellent communication skills to interact effectively with clients and vendors, demonstrate leadership qualities, and be able to work collaboratively with the team. Ideal candidates must hold a Bachelor's degree in Mechanical Engineering, Electrical Engineering, or a related field. Moreover, having expertise in Design Engineering, Product Design, Computer-Aided Design (CAD), strong problem-solving abilities, and experience in the automation industry would be advantageous. The role may require on-site work in the Pune/Pimpri-Chinchwad area.,

Qualcomm India Private Limited is a leading technology innovator in the Engineering Group, specifically in Hardware Engineering. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems. This includes circuits, mechanical systems, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop solutions. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 6 years of Hardware Engineering experience. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience is also acceptable. As a CPU Physical Design Methodology Engineer, you will work with implementation and CAD teams to achieve aggressive power, area, and performance goals using industry standard tools/flows for next-generation CPUs. The ideal candidate will possess a Bachelor's/Master's degree in Electrical Engineering with at least 5 years of practical experience. Proficiency in synthesis, place and route, signoff timing/power analysis, and knowledge of high-performance and low-power implementation techniques is required. Strong scripting skills in TCL, Python, and Perl are also necessary. Preferred qualifications include experience in deep submicron process technology nodes, knowledge of library cells and optimizations, and familiarity with industry standard tools for synthesis, place & route, and tapeout flows. Good data analytical skills for identifying and resolving physical design issues are highly valued. As a Physical Design Methodology Engineer, your responsibilities will involve collaborating with cross-functional teams to solve key physical design problems in CPU implementations. You will develop innovative techniques in physical design and optimization space to meet aggressive PPA targets, work with external CAD tool vendors and internal CAD teams to improve optimization issues, and analyze, implement, and enhance optimization methods for designs. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations are available upon request to support participation in the hiring process. Employees are expected to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking jobs at Qualcomm. Unsolicited submissions from agencies or individuals represented by agencies are not authorized. For more information about this role, please contact Qualcomm Careers.,

As a Specialist in Industrial Engineering, you will be responsible for designing the Production Assembly line/SPM to ensure it meets Capacity, Quality, Safety, and Ergonomic requirements. Supporting the Indian Manufacturing group, you will focus on specific high-tech areas such as SPM Building, Lean Manufacturing, Ergonomics, Cost analysis, and Process Management within the plant. Your expertise in welding technologies including Resistance Welding, Laser Welding, TIG/MIG Welding, and Welding Technology for Electrical Contacts will be crucial. You will be involved in specifying, implementing, and qualifying the Manufacturing Process & Equipment in compliance with SPS Principles, as well as introducing and standardizing new assembly technologies/processes locally. Key responsibilities will include developing new layouts, improving current layouts, providing vendor support functions, implementing Lean Manufacturing practices, executing cost reductions, and leading new projects. Your role will also involve collaborating with the local industrialization team or local manufacturing Engineering team to design assembly and manufacturing lines, prepare Manufacturing Process Specification documents, and provide technical solutions based on customer and product requirements. You will play a vital role in ensuring the feasibility of Product Assembly for new offers and contributing to Continuous Improvement actions for Process & Equipment. Your expertise in Product Selections including Conveyor selections, Pneumatics, Robots Integration, Pick and Place systems, Servo slides Selection, Tooling & testing equipments, Gluing, UV Curing, Bowel feeder & Tightening Equipment selection, Welding, Laser Marking & Camera Inspections will be utilized for innovative, precise, and cost-effective solutions. Proficiency in AutoCAD, Autodesk Inventor, and experience with Product and Process Design FMEA are essential qualifications for this role. A Bachelor's degree in Mechanical or Industrial Engineering with 10-12 Years of experience is required. This is a full-time position based in Hyderabad, Telangana. If you are a processional with a passion for industrial engineering and a drive for continuous improvement, we invite you to consider joining our team.,

As the Wire Bonding/Flip Chip Packaging Engineering, you will be responsible for developing technology and processes related to FOL (Front of Line) and EOL (End of Line) stages. This includes tasks such as back grinding, laser groove, mechanical sawing, SMT & Flip Chip Attach, mass reflow/TCB/fluxless, flux cleaning, plasma clean, underfill, mold underfill, ball attach, saw singulation, O/S, FVI, pick and place, and packing. Your role will involve understanding, integrating, and innovating solutions to meet customer packaging requirements in a cost-effective manner. You will be required to initiate technical discussions with vendors to gather relevant data and complete initial analyses for decision-making. Additionally, you will participate in the selection of methodologies, materials, manpower, and machines based on performance and past experiences. Installing, verifying, and qualifying processes and products for development, New Product Introduction (NPI), and Low Volume Manufacturing (LVM) will also be part of your responsibilities. Your continuous focus should be on achieving the highest degree of packaging difficulty while ensuring ease of Design for Manufacturability (DFM) to meet customer expectations for quality, yield, and output. You will need to offer a diverse range of Bill of Materials (BOM) selections to accommodate various customer requirements and execute multiple department projects effectively. To excel in this role, you should hold a relevant engineering or science degree and have experience in leading teams to achieve organizational goals. Proficiency in MS Office, 8D writing, Design of Experiments (DOE), Statistical Process Control (SPC), Failure Modes and Effects Analysis (FMEA), Out of Control Action Plan (OCAP), and Control Plan is essential. A strong passion for innovation and continuous learning to achieve the seemingly impossible will be crucial for success in this position.,

As an ASIC Digital Design Engineer at Synopsys, you play a crucial role in designing and developing high-performance digital designs at both chip and block levels. Your robust understanding of digital design principles and experience in RTL coding and simulation are key to driving the success of cutting-edge silicon chips that power innovative applications. Collaborating with verification teams, you ensure thorough testing and validation of designs while analyzing and optimizing design performance, power, and area metrics. Your proactive problem-solving skills and detail-oriented approach enable you to contribute effectively in design reviews, providing constructive feedback to peers. Working closely with physical design teams, you ensure seamless integration and tape-out success, enhancing the efficiency and performance of digital design processes. Staying updated with the latest industry trends, you integrate new methodologies and tools into the design process, influencing the adoption of new technologies within the team. You are a detail-oriented professional committed to delivering high-quality work, with excellent communication skills to articulate complex concepts clearly and concisely. As a collaborative team player, you thrive in a multidisciplinary environment, bringing a can-do attitude to drive projects to success. Your adaptability and openness to learning new tools and technologies make you a valuable asset in supporting continuous improvement of design practices and standards across the organization. Joining the ASIC Digital Design team at Synopsys, you become part of a group dedicated to innovation and continuous learning. Together, we tackle challenging projects, leveraging our expertise to push the boundaries of what's possible in high-performance digital solutions. You will have the opportunity to work in a supportive and inclusive environment, where diversity is valued and contributions are recognized. In addition to the rewarding work you will be doing, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically within the Hardware Engineering department. In this role, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. Your work will involve a wide range of tasks including bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to facilitate the launch of cutting-edge, world-class products. Collaboration with cross-functional teams is crucial to develop solutions and meet performance requirements effectively. To be considered for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. Additionally, candidates are expected to possess a degree from a top-tier institute and have 8-14 years of experience in physical design from product-based companies. The ideal candidate should have proven experience in managing complex subsystems and small teams. Proficiency in complete Netlist2GDS, including Floorplan, place and route (PnR), and sign-off convergence, along with experience in lower technology nodes, is essential. Furthermore, expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration is required. Experience in low power design implementation, familiarity with ASIC design flows and physical design methodologies, and a strong understanding of circuit design, device physics, and deep sub-micron technology are also critical for success in this role. Additionally, the successful candidate should have experience working on multiple technology nodes in advanced processes and proficiency in automation to drive improvements in PPA. The role will involve managing and driving a small team for project execution and PPA targets. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For accommodation during the application/hiring process, individuals can contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Submissions from agencies or individuals represented by agencies will not be considered. Unsolicited resumes or applications will not be accepted. For more information about this role, interested individuals can reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: - Bachelors or Masters degree from a top-tier institute. - 2-5 years of experience in physical design from product-based companies. Experience: - Proven experience in managing complex subsystems and small teams. - Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements: - Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. - Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. - Familiarity with ASIC design flows and physical design methodologies. - Strong understanding of circuit design, device physics, and deep sub-micron technology. - Experience working on multiple technology nodes in advanced processes. - Proficiency in automation to drive improvements in PPA. Qualcomm is an equal opportunity employer and is committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of company confidential information. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams to develop solutions and meet performance requirements is a key aspect of the role. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the relevant field is also acceptable. Candidates with Bachelors or Masters degrees from top-tier institutes and 3 to 10 years of experience in physical design from product-based companies with some leadership experience are preferred. Applicants should have proven experience in managing complex subsystems and small teams, as well as proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration is essential. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating is also required. Familiarity with ASIC design flows and physical design methodologies, a strong understanding of circuit design, device physics, and deep sub-micron technology, as well as experience working on multiple technology nodes in advanced processes are desired qualifications. Proficiency in automation to drive improvements in PPA is a key skill for this role. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, you may contact Qualcomm via email at disability-accomodations@qualcomm.com or through their toll-free number. Qualcomm expects its employees to abide by all applicable policies and procedures, including those related to security and the protection of company confidential information. Please note that Qualcomm's Careers Site is for individuals seeking a job directly at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited resumes or applications from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. You should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. We are seeking bright ASIC design engineers with excellent analytical and technical skills to be part of a fast-paced team responsible for delivering Snapdragon CPU design for high-performance SoCs in sub-10nm process for Mobile, Compute, and IOT market space. In this role, you will participate in projects involved in the development of ASICs, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will create design experiments, perform detailed PPA comparison analysis, work closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Key Responsibilities: - Develop Place & Route recipes for optimal PPA - Tabulate metrics results for analysis comparison - Complete ASIC flow with low power, performance, and area optimization techniques - Experience with STA using Primetime and/or Tempus - Proficient in constraint generation and validation - Knowledge of multiple power domain implementation with complex UPF/CPF definition - Formal verification experience (Formality/Conformal) - Skills in Perl/Tcl, Python, C++ - Strong problem-solving and ASIC development/debugging skills - Experience with CPU micro-architecture and their critical path - Low power implementation techniques experience - High-speed CPU implementation - Clock Tree Implementation Techniques for High Speed Design Implementation - Exposure to Constraint management tool and Verilog coding experience Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a passionate and skilled Hardware Engineer to join our Engineering Group. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To be considered for this role, you should hold a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with 1-3+ years of Hardware Engineering experience. We are particularly interested in individuals with ASIC design expertise and strong analytical skills. This is a fantastic opportunity to contribute to the development of Snapdragon CPU design and high-performance SoCs in the Mobile, Compute, and IOT market space. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be required to conduct detailed analysis to improve results, optimize Performance, Power, and Area (PPA), and collaborate closely with various teams to achieve project goals. Proficiency in tools such as FC, Innovus, Primetime, Tempus, and languages like Perl, Tcl, Python, and C++ is highly desirable. Your role will involve developing Place & Route recipes for optimal PPA, managing constraints, and ensuring the implementation of low power techniques. Experience with CPU micro-architecture, clock tree implementation, Verilog coding, and formal verification will be valuable assets. Strong problem-solving skills and a dedication to ASIC development and debugging are essential in this role. Qualcomm is an equal opportunity employer committed to providing a supportive and accessible work environment for individuals with disabilities. If you require accommodations during the application process, please contact us at disability-accommodations@qualcomm.com. We expect all employees to adhere to company policies and procedures, including maintaining the confidentiality of proprietary information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through our Careers Site. For further inquiries about this position, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and top levels for industry-leading CPU core designs, emphasizing scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Working on cutting-edge technology nodes and applying advanced physical design techniques to enhance CPU performance and efficiency is a key aspect of this role. Key responsibilities include driving floorplan architecture and optimization in collaboration with PD/RTL teams, engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams, partnering with EDA tool vendors and internal CAD teams for improved design efficiency, making strategic trade-offs in design decisions to achieve optimal PPA outcomes, and ensuring end-to-end Physical verification closure for subsystem. The ideal candidate will have experience in physical design including floor-planning, placement, clock implementation, and routing for complex, big, and high-speed designs. Knowledge of physical synthesis and implementation tools such as Cadence Innovus/Genus and Synopsys Fusion Compiler is preferred, along with a good understanding of CMOS circuit design, static timing analysis, reliability, and power analysis. Strong collaboration skills, innovative thinking for power and performance improvements, scripting skills, and expertise in Physical Verification flow are required. Preferred skills for this role include clock implementation, power delivery network design choices, process technology knowledge, experience in flow and methodology development, hands-on experience with Synthesis, DFT, Place and Route, and Timing and Reliability Signoff. Interaction with design and architecture teams, working with sub-micron technology process nodes, and prior experience in flow and methodology development are advantageous. Minimum qualifications include a Bachelor's degree in Electrical/Computer Engineering, 8+ years of direct top-level floor-planning experience, a strong background in VLSI design, physical implementation, and scripting, as well as experience working with industry-standard Synthesis and Place and Route tools. Self-motivation, time management skills, and a commitment to abide by all applicable policies and procedures are expected from applicants. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems within ASIC/SoC design. Your focus will be on achieving robust timing closure and optimizing physical implementation in terms of power, performance, and area. Your role will involve developing and refining methodologies for STA and PNR specifically tailored to address the challenges posed by large, multi-interface, or mixed-signal subsystems. You will drive automation and validation of timing and physical design data across subsystem boundaries to ensure seamless integration. As a key member of the team, you will mentor and guide junior engineers, fostering their technical growth and promoting knowledge sharing within subsystem teams. Collaboration across functions to address design, timing, and physical implementation challenges unique to complex subsystem integration will be a crucial aspect of your responsibilities. Your excellent communication skills will be essential for presenting technical solutions and leading discussions with internal teams and customers, especially in relation to subsystem-level trade-offs and integration. To be successful in this role, you should have at least 10 years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including expertise in advanced technology nodes (7nm or below). Proficiency in tools such as Synopsys PrimeTime, Cadence Tempus for STA, and Synopsys ICC2, Cadence Innovus for PNR applied to large, multi-block, or hierarchical subsystems is required. Experience in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems will be advantageous. Background knowledge in high-speed interfaces or mixed-signal SoC subsystems is preferred. Join Renesas to be a part of a global team dedicated to building a sustainable future where technology enhances lives and shapes the world of electronics. Let's shape the future together at Renesas.,

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

As an ASIC Physical Design Engineer at Synopsys, you will play a key role in driving innovations that shape the future of technology. Your expertise in delivering high-quality, timing-clean designs will be essential in empowering the creation of high-performance silicon chips and software content. You will be responsible for owning the complete physical implementation process at both block and chip levels, ensuring DRC, LVS, and IR closure, and collaborating closely with the frontend design team to resolve design issues. Your role will involve delivering timing-clean blocks and chip-level designs that meet specified targets, evaluating and setting up physical design flows, and managing all chip-level tasks including P&R, STA, PV, and IR. Your proficiency in scripting with Tcl and Perl will enhance your ability to optimize design flows and achieve project goals efficiently. Additionally, you will contribute to the successful delivery of high-performance silicon chips, enhance the efficiency and reliability of physical design processes, and drive innovation in chip design and integration. To excel in this role, you will need an MSEE/BSEE with 5+ years of related experience in ASIC physical design, in-depth understanding of physical design specialization, strong problem-solving skills, and experience with scripting languages such as Tcl and Perl. Your ability to mentor junior engineers, collaborate effectively in team-driven projects, and network with senior personnel will be crucial in strengthening Synopsys" reputation as a leader in semiconductor technology. Joining our dynamic and innovative team, you will have the opportunity to push the boundaries of chip design and integration. Together, we focus on delivering high-performance silicon chips through collaborative efforts and cutting-edge technologies. We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

You will be responsible for the technology and process development of Flip Chip product packaging, including tasks such as Back grinding, Laser groove, Mechanical sawing, SMT & Flip Chip Attach, Mass Reflow/TCB/Fluxless, Flux Cleaning, Plasma Clean, Underfill, Mold Underfill, Ball Attach, Saw Singulation, O/S, FVI, Pick and Place & Packing. Your role will involve understanding, integrating, and innovating to meet customers" packaging requirements with a cost-competitive DFM solution. You will initiate and participate in technical discussions with vendors to gather relevant data, conduct initial analysis, and submit final decision submissions. Your involvement will also include selecting 4Ms based on performance and previous experience, installing, buying-off, and qualifying processes and products for development, NPI, and LVM. Your primary focus will be on meeting the highest degree of packaging difficulty, ensuring ease of DFM, achieving the best customer desired outputs, best-in-class Yield, and maintaining industry-best Quality. You will offer a wide range of BOM selections to meet different customer requirements and execute multiple department projects. You will be responsible for identifying all process controls requirements, using BKM for inputs & outputs data gathering/controls, and assisting in the MES, Automation of material, process, and recipe controls. The position requires a minimum relevant engineering or Science degree, with a minimum of 4 years of total experience for Sr Engineer or 8 years for Section Manager. Experience in leading a group or team of employees to achieve organizational goals is essential, along with exposure to MS Office, 8D writing, DOE, SPC, FMEA, OCAP, and Control Plan. A passion for achieving the seemingly impossible through innovation and continuous learning is highly valued.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

As a Silicon Design Engineer 2 at AMD, you play a crucial role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Your responsibilities include interfacing with large, globally distributed design teams to support complex and collaborative development efforts. You will drive automation of Synthesis, Place and Route, Logic Eqv, and Functional ECO methodologies targeting advanced technology nodes. Additionally, you will be responsible for developing and automating Synthesize, PnR, and Functional ECO for various designs at advanced technology nodes and scripting out utilities to automate different components of the implementation flow. Your role will involve collaborating closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. You will contribute to the evolution of AMD's design infrastructure by improving automation, performance, and methodology robustness. Hands-on experience in Front-End Synthesis, Logical Eqv, and Conformal ECO flows is essential, along with proficiency in industry-standard tools such as DC, Fusion Compiler, FM, VCLP, ICC2, Innovus, and Conformal. Experience in PnR, STA, Formal Verification, or RTL coding domains is a plus. An automation mindset and expertise in CAD flow and methodology development on advanced process nodes are preferred. To qualify for this role, you should hold a Master's degree in Electronics Engineering and possess 3-6 years of experience in CAD flow and methodology development on advanced nodes. Proficiency in scripting languages like Python, Tcl, Perl, sed/awk is required. Strong problem-solving skills, analytical thinking, and excellent communication skills are essential. As a team player with a good work ethic, you will thrive in a collaborative environment. This position is based in Hyderabad. If you are looking to be part of a team that pushes the limits of innovation to solve the world's most important challenges, AMD could be the perfect place for you to advance your career in silicon design engineering.,

Design and develop integrated circuits, overseeing the definition, design, verification, and documentation for ASIC development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyze equipment to establish operation data, conduct experimental tests, and evaluate results. Also, review vendor capability to support development. Utilize wide-ranging experience and professional concepts to resolve complex issues creatively and effectively. Possess strong project management skills and lead the design and delivery of new products/processes. Demonstrate functional breadth and depth, as well as expertise in complementary fields. Apply broad concepts and theories to achieve innovative and effective solutions to complex problems. Work on complex issues requiring an in-depth evaluation of variable factors. Exercise judgment in selecting methods, techniques, and evaluation criteria for obtaining results. Network with key contacts outside own area of expertise. Champion significant projects, programs, and business initiatives using creativity and ingenuity. Lead major projects and influence or impact others" priorities, decisions, or activities. Serve as an escalation point for complex issues and coach and mentor other junior team members. Provide leadership for the work group through knowledge in the area of specialization. Determine work priorities based on general direction from managers. Determine methods and procedures on new assignments. Consult with management on long-range goals. Set own priorities, both tactical and strategic. Bachelor's degree and 8+ years of related experience; at this level post-graduate coursework may be desirable. Alternatively, a Master's degree and 6+ years of related experience or a PhD and 3+ years of related experience.,

Qualcomm India Private Limited is seeking a talented Hardware Engineer to join their Engineering Group under the Hardware Engineering division. As a part of Qualcomm, a leading technology innovator, you will play a crucial role in designing, optimizing, and testing electronic systems to contribute to the development of cutting-edge, world-class products. Collaborating with cross-functional teams, you will work towards creating solutions that meet performance requirements and drive digital transformation in the smart, connected future. To qualify for this position, you should hold a Bachelor's or Master's degree from a prestigious institute and possess a minimum of 6 to 10 years of experience in physical design within product-based companies. The ideal candidate will have proven expertise in managing complex subsystems and small teams, along with proficiency in RTL2GDS, including Floorplan, place and route (PnR), and sign-off convergence. In this role, you will be responsible for meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems and System on Chips (SoCs), as well as low power design implementation. Your tasks will include working on multiple technology nodes in advanced processes, ensuring power gating, and driving improvements in PPA through automation. Additionally, you will be expected to lead a small team for project execution and achieving PPA targets. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you may contact Qualcomm via email at disability-accommodations@qualcomm.com or through their toll-free number. As an employee of Qualcomm, you are expected to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this exciting opportunity, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,

As an Integrated Circuit Designer, you will be responsible for overseeing the definition, design, verification, and documentation for ASIC development. Your role will involve determining architecture design, logic design, and system simulation. You will be defining module interfaces/formats for simulation and contributing to the development of multidimensional designs involving the layout of complex integrated circuits. Additionally, you will evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzing equipment to establish operation data, conducting experimental tests, and evaluating results will also be part of your responsibilities. You may also be involved in reviewing vendor capability to support development. You should have wide-ranging experience and use professional concepts and company objectives to resolve complex issues in creative and effective ways. Strong project management skills are essential for this role. Leading the design and delivery of new products/process and being expert in complementary fields are key aspects of this position. You will be applying broad concepts and theories to achieve innovative and effective solutions to complex problems. In this role, you will work on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. You will exercise judgment in selecting methods, techniques, and evaluation criteria for obtaining results. Networking with key contacts outside your area of expertise will be necessary. Championing significant projects, programs, and business initiatives using demonstrated creativity and ingenuity is expected from you. You will be a team leader, leading major projects, influencing or impacting others" priorities, decisions, or activities. You will also serve as an escalation point for complex issues and coach and mentor other junior team members. As a team leader, you will provide a leadership role for the work group through knowledge in your area of specialization. You will be generally free to determine work priorities based on general direction from managers. Determining methods and procedures on new assignments, consulting with management on long-range goals, and determining your own priorities, both tactical and strategic, will be part of your responsibilities. To qualify for this position, you should have a Bachelor's degree and 8+ years of related experience. Alternatively, a Master's degree and 6+ years of related experience or a PhD and 3+ years of related experience would also be considered. Post-graduate coursework may be desirable at this level.,