61 Place Jobs

As a Digital Physical Design Engineer, you will play a crucial role in the physical implementation of complex digital integrated circuits. Your responsibilities will include: - Execute physical design activities such as floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). - Perform physical verification (DRC, LVS, Antenna) and address related issues efficiently. - Conduct power integrity analysis focusing on IR drop and EM, and optimize designs for enhanced power efficiency. - Participate in design-for-test (DFT) implementation and ensure the verification of test structures. - Collaborate closely with design, verification, and DFT teams to e...

You will be part of a team responsible for creating Design Methodology solutions for various Technology nodes, focusing on developing Digital design enablement collateral to assist GLOBALFOUNDRIES customers in adopting advanced silicon technologies (12/14/22/28/40/55). Your specific responsibilities include: - RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing, and Physical Verification - Collaborating closely with EDA vendors and PDK to define, implement, customize, and qualify digital design flows - Using TCL, Python, Pandas, and Google APIs for automation in flow regressions, error/warning collection, and key design metrics comparison to ensure high...

As an experienced Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design of ASICs, ensuring successful execution from netlist to GDS2. Your expertise in ASIC designs Place and Route flow, low-power methodologies, and PnR tools like Innovus/Fusion compiler will be crucial in this role. Your ability to debug Congestion and CTS issues, as well as familiarity with Sign-off methodology and tools, will be essential for ensuring the quality of the final product. Key Responsibilities: - Thorough knowledge and hands-on experience in ASIC designs Place and Route flow and methodology - Execute complete PD ownership from netlist to GDS2, including HM level P...

As a Place and Route Engineer at our company in Hyderabad, you will be responsible for supporting Place and Route flows for various designs at 6nm, 4nm, and 3nm technology nodes. Your key responsibilities will include: - Qualifying tool versions and deploying new features into the flow - Updating existing flows for new capabilities as required - Utilizing hands-on experience in Synopsys Fusion Compiler or ICC2 - Demonstrating proficiency in scripting languages like PERL, TCL, and possessing strong debug capabilities - Applying hands-on experience in synthesis, place and route flows, and STA tools - Utilizing hands-on experience with physical verification tools such as PnR flow qualification,...

As a Hardware Engineer at Qualcomm India Private Limited, your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Perform Physical Implementation activities for high-performance Cores for various technologies such as 16/14/7/5nm or lower - Tasks may include floor-planning, place and route, clock tree synthesis, for...

Role Overview: You will be responsible for the technology and process development for Wire Bonding/Flip Chip packaging engineering. This includes FOL processes such as Back grinding, Laser groove, Mechanical sawing, SMT & Flip Chip Attach, Mass Reflow/TCB/Fluxless, Flux Cleaning, Plasma Clean, Underfill, and EOL processes like Mold Underfill, Ball Attach, Saw Singulation, O/S, FVI, Pick and Place & Packing. Your role will involve understanding, integrating, and innovating to meet customers" packaging requirements into a cost-competitive DFM solution. You will initiate and engage in technical discussions with vendors to gather relevant data, review and complete initial analysis for final deci...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cade...

You will be responsible for supporting Place and Route flows for various designs at 6nm, 4nm, and 3nm technology nodes. This includes tool versions qualification and deployment of new features into the flow. You will also be updating existing flows for new capabilities as required. It is essential to have hands-on experience in Synopsys Fusion Compiler or ICC2, along with good control over scripting languages like PERL, TCL, and strong debug capabilities. Additionally, hands-on experience in synthesis, place and route flows, and STA tools is required. You will also need hands-on experience with physical verification tools, PnR flow qualification, running multiple PnR blocks to benchmark QOR,...

As a staff FPGA/SoC integration engineer at Microchip Technology Inc., you will play a crucial role in integrating all custom and external IPs into the FPGA top. Your responsibilities will include owning the chip top RTL, place/route, timing closure, and other deliverables required for the production release of the FPGA. **Key Responsibilities:** - Develop flows and methodologies to enhance the integration of complex IPs into the FPGA chip-top using the digital-on-top (DoT) approach. - Create tools and scripts (RTL and custom scripts) to verify connectivity and functionality of the chip-top. - Manage chip-level floorplan activities, place and route, timing closure, and physical and electrica...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be part of the Engineering Group, focusing on Hardware Engineering. Your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements, pushing the boundaries of technology to enable next-generation experiences. Key Responsibilities: - Plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems - Collaborate with ...

Role Overview: At Synopsys, we drive innovations in chip design, verification, and IP integration to shape the future through continuous technological innovation. As an ASIC Digital Design Engineer, you will be designing and developing high-performance digital designs at chip and block levels, collaborating with cross-functional teams, and ensuring the success of key projects through your technical expertise. Key Responsibilities: - Designing and developing ASIC RTL for high-performance digital designs - Collaborating with verification teams for testing and validation - Analyzing and optimizing design performance, power, and area metrics - Participating in design reviews and providing constr...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - Manage complex subsystems and small teams effectively - Proficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence, including S...

As a leading technology innovator, Qualcomm India Private Limited pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. **Roles and Responsibilities:** - Work with cross...

Role Overview: As a Backend (Physical Design) Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconductor designs. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initi...

As a Mechanical Design Engineer specializing in Automation, your role involves designing mechanical engineering components, developing Special Purpose Machines (SPM), and reviewing 2D detail drawings. You will be a key resource in a team environment for mechanical design and development, working closely with cross-functional teams to meet customer requirements and propose optimized solutions. Key Responsibilities: - Experience in automation, electromechanical/mechatronics, and related concepts. - Understanding customer requirements and proposing feasible ideas and concepts. - Proficiency in creating, reading, and interpreting engineering drawings and standards, especially for precision compo...

As an experienced SoC Physical design engineer, you should have a minimum of 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. It is essential that you possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the lat...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

As a Physical Design Engineer specializing in Place and Route (PnR) with 5-8 years of experience, your role will involve the following responsibilities: - Implementing physical design of integrated circuits - Performing place and route activities to meet performance, area, and power targets - Collaborating with cross-functional teams for successful tape-out Your qualifications should include: - Bachelor's or Master's degree in Electrical/Electronics Engineering or related field - Proficiency in industry-standard EDA tools for place and route - Strong understanding of physical design methodologies Please note that the job is based in Bangalore and is a full-time position.,

Role Overview: As a member of the team, you will be part of a group dedicated to pushing boundaries and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a key role in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products loved by millions worldwide. Key Responsibilities: - Develop all aspects of RTL2GDS for ASIC/Mixed signal chips. - Take complete ownership of physical design integration and CAD flow for Mixed signal chip development. - Drive the closure of timing and power/Physical convergence of the design. - Contribute to physical design methodologies and automation ...

Job Description: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Your role will require collaboration with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Demonstrating good knowledge of CMOS technology and physical design concepts such as flooplanning, place and route, clock tree synthesis (CTS), physical verification, and static timing analysis (STA). - Taking responsibility for developing CAD tool/flow solutions w...

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. **Key Responsibilities:** - Manage complex subsystems and small teams effectively. - Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off ...

As an ASIC Physical Design Lead, you will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. Key Responsibilities: - Lead the physical design of complex ASIC projects from Netlist to GDSII. - Perform timing closure tasks including synthesis, place and route, and static timing analysis. - Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. - Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. - Mentor junior engineers and gui...

As an experienced Physical Design Engineer, you will be responsible for executing block level P&R and Timing closure activities. Your primary role will involve owning up block level P&R and performing Netlist2GDS on blocks. You will be working on the implementation of multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. Your expertise should cover various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal I...

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Manage complex subsystems and small teams effectively - Demonstrate proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations - Ensure meeting demanding Power, Performance, and...