10 Timing Convergence Jobs

In this role, you will be leading all block/chip level physical design activities. This includes tasks such as generating floor plans, abstract views, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. Collaboration with the design team to address design challenges will be a key aspect of this position. You will also be assisting team members in debugging tool/design related issues and constantly seeking opportunities to enhance the RTL2GDS flow to improve power, performance, and area (PPA). Troubleshooting various design issues and applying proactive interventions will be part of your responsibilities. Your main responsibility will be overseeing all aspects of physical design and implementation of GPUs and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 3 years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 2 years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 1 year of Hardware Engineering or related work experience. What We Need To See: - Strong experience in Physical Design. - Proficiency in RTL2GDSII flow or design implementation in leading process technologies. - Good understanding of concepts related to synthesis, place & route, CTS, timing convergence, and layout closure. - Expertise in high frequency design methodologies. - Knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. - Working experience with tools like ICC2/Innovus, Primetime/Tempus, etc., used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Familiarity with timing constraints, STA, and timing closure. - Proficiency in automation skills in PERL, TCL, tool-specific scripting on industry-leading Place & Route tools. - Ability to multitask and work in a global environment with flexibility. - Strong communication skills, motivation, analytical & problem-solving skills. - Proficiency in using Perl, Tcl, Make scripting is preferred. As you consider your future career growth, we invite you to explore the opportunities our organization can offer you.,

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required for this role. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. Proficiency in Tcl/Perl Scripting and strong problem-solving skills, along with effective communication skills, are vital for this position. Qualcomm India Private Limited is seeking candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in a relevant field and 1+ year of Hardware Engineering experience, or a PhD in a related field, are also acceptable qualifications. The ideal candidate should have 1-3 years of experience in Physical Design/Implementation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to security and the protection of Company and proprietary information. It is essential to ensure workplace accessibility for individuals with disabilities. For further information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes a wide range of tasks such as bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. The ideal candidate for this position must have a minimum of 8+ years of relevant experience. Key qualifications and responsibilities include: - Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0-cycle, multi-cycle path handling. - Hands-on experience with STA tools such as Prime-time and Tempus. - Experience in driving timing convergence at Chip-level and Hard-Macro level. - In-depth knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed-through handling. - Knowledge of ASIC back-end design flows and methods and tools like ICC2, Innovus. - Proficiency in scripting languages such as TCL, Perl, Awk. - Basic knowledge of device phy. - Familiarity with Spice simulation tools like Hspice/FineSim, Monte Carlo, and Silicon to spice model correlation. - Experience in design automation using TCL/Perl/Python. - Familiarity with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus. - Ability to work on automation scripts within STA/PD tools for methodology development. - Good technical writing and communication skills, with a willingness to work in a cross-collaborative environment. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For accommodation during the application/hiring process, individuals can email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security requirements regarding protection of confidential information. Note: Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through Qualcomm's Careers Site. Unsolicited submissions will not be considered. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. The ideal candidate for this role should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. Additionally, you should have 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects. A solid understanding of industry-standard tools such as PT, Tempus, and familiarity with PNR tools like Innovus/FC is required. Proficiency in fixing STA aspects to solve extreme critical timing and clock path analysis is essential. Experience in preparing complex ECOs for timing convergence across a wide range of corners through Tweaker, Tempus, Physical PT ECOs, and manual ECOs is highly valued. Candidates with experience in deep submicron process technology nodes, particularly below 10nm, are strongly preferred. Knowledge of high-performance and low-power interface timing is considered an added benefit. A strong grasp of basic VLSI design concepts, synchronous design timing checks, and understanding of constraints is necessary. Proficiency in Unix, TCL, PT-TCL, Tempus-TCL scripting is required, with familiarity with Python background being an added bonus. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. For accommodation requests, individuals may contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to security and the protection of confidential information. Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. For more information about this role, please contact Qualcomm Careers directly.,

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ips for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . Show more Show less

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of Hardware Engineering experience. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience will also be considered. As a Hardware Engineer at Qualcomm, you should have 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects. A solid understanding of industry-standard tools like PT, Tempus, GENUS, Innovus, and ICC is required. You should also possess expertise in STA fixing aspects to solve extreme critical timing bottleneck paths and preparing complex ECOs for timing convergence across a wide range of corners using tools like Tweaker, Tempus, or Physical PT ECOs. Experience in deep submicron process technology nodes is preferred, along with knowledge of high-performance and low-power implementation methods. You should be willing to push PPA to the best possible extent and have a strong grasp of fundamentals. Expertise in Perl and TCL languages is also required for this role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodation during the application/hiring process, you can reach out to Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm, and unsolicited submissions from staffing and recruiting agencies will not be accepted. For more information about this role, you can contact Qualcomm Careers directly.,

#HCLTech is seeking a skilled Physical Design Engineer for an exciting opportunity! Key Requirements: - 5+ years of experience in Timing analysis, timing convergence, SI/Noise analysis, and Signoff quality - Proficiency in multi-voltage scenarios design and STA closure on Low power designs - Familiarity with industry standard EDA tools like Primetime - Hands-on experience in Physical Design implementation is a bonus - Skill in scripting languages such as Perl and Tcl for automation - Knowledge of 16/14/10/7/5nm nodes - Understanding of computer organization/architecture is advantageous - Strong problem-solving abilities and attention to detail - Excellent communication skills and ability to collaborate across diverse teams Join us at #HCLTech for this challenging opportunity in Physical Design Engineering! #EngineeringJobs #fullchiptiming Send your resumes to [HIDDEN TEXT] Show more Show less

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

As the SOC Verification Lead, you will be responsible for coordinating with SOC (Design, DFT, PD), System, and SW engineering teams to drive and lead SOC verification execution. You will take ownership of multiple SOC verifications within the targeted functional domain. Your role will involve collaborating with customers on feature requirements, use case scenarios, and test plan reviews to ensure that the SOC meets all functional aspects of the targeted domain. Additionally, you will work closely with the architecture and design team on high-level architecture and use case scenarios, as well as the configuration space. Collaboration with the IP team for IP requirements and deliverables will be a key aspect of your responsibilities. You will also engage with vendors and ODC members to ensure successful project execution. Your role will require working with the program management team on SOC planning, schedule management, resource demand/supply, critical path analysis, development cost, and execution. Furthermore, you will collaborate with the post-Si team to drive Si bring-up and ramp to productization. As a Pattern Verification Manager, you will leverage your expertise in Patterns/Crest functional domains. Your duties will include developing patterns, verifying them, and delivering patterns to the Product Engineering team for silicon validation. You will be responsible for creating test plans for the patterns at the SOC level, and ensuring they are reviewed with stakeholders. Collaboration with the IP design team for IP requirements and deliverables, as well as working with the program management team for Patterns planning, schedule management, critical path analysis, and execution, will also be part of your responsibilities. You will be driving SOC verification from feature extraction to tape-out and productization. Adapting to design changes, leading Verification Architecture, test-plan creation, power reduction, timing convergence, test bench and test plan reviews, and tape-outs will be crucial aspects of your role. Running regular execution meetings, scrums, standing meetings, and resolving bottlenecks will be essential for successful project outcomes. Additionally, you will be involved in project planning, including scheduling, deliverables, risk assessment, and mitigation strategies. Your leadership will be pivotal in driving the team towards bug-free silicon deliverables.,

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our lifes work , to amplify human creativity and intelligence. As an NVIDIAN, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What You'll Be Doing In this position, you will expected to develop and support flows & scripts based around industry standard PnR EDA tools Work in collaboration with PD team for addressing design challenges Help team members in debugging tool/flow related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. What We Need To See BE/BTECH/MTECH, or equivalent experience. 4+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to place & route, CTS, timing convergence, layout closure. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Good automation skills in PERL, TCL, Python and tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Widely considered to be one of the technology worlds most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. , , JR1995590,