4 Synopsys Icc2 Jobs

KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details.

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurturing their technical growth and promoting knowledge sharing within subsystem teams. Collaboration with various cross-functional teams will be essential to resolve design, timing, and physical implementation challenges that are specific to the integration of complex subsystems. Your qualifications should include a minimum of 10 years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, with expertise in advanced technology nodes such as 7nm or below. Proficiency in STA tools like Synopsys PrimeTime, Cadence Tempus, and PNR tools such as Synopsys ICC2, Cadence Innovus for application in large, multi-block, or hierarchical subsystems is required. A proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be skilled in scripting languages like Tcl, Perl, Python for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience in collaborating across frontend, physical design, and verification teams to integrate complex subsystems are crucial. Previous experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level would be advantageous. A background in high-speed interfaces or mixed-signal SoC subsystems is preferred for this role.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc.