9 Synopsys Icc2 Jobs

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow s...

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...

KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Ment...

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and ...

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurtur...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Physical Design Manager role managing team of 10+ members for SOC designs. Key Responsibilities :- Manage Synthesis, Physical Design, and timing teams Lead internal and external resources Ensure SOC chip completion on schedule Oversee Physical implementation Guide Synthesis and Power Reduction efforts Handle complex SOC management Work with 7nm and sub-7nm projects Manage Full Chip Floor planning Ensure on-time delivery Drive improvements and problem-solving Qualifications & Skills Education:- BE/B.Tech/ME/M.TECH in ECE/EEE Experience:- 12+ years (3+ years in people management) Skills: -Team management, technical problem solving, Communication skills, Presentation skills, Tool expertise (Syn...