Posted:2 weeks ago|
Platform:
On-site
Full Time
Physical Design Engineer (PD/STA/Synthesis) Must-Haves: • Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA • Flow Experience: • Floorplanning • Power planning • Placement • Clock Tree Synthesis (CTS) • Routing • Physical Verification (DRC/LVS) • Timing Closure • Knowledge of: • Low-power design (UPF/CPF) • ECOs • IR Drop, EM Analysis • STA constraints and timing analysis Nice-to-Haves: • Experience with block-level and/or full-chip PD • Familiarity with scripting (Tcl, Perl, Python) Show more Show less
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