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Skills Required

planning routing timing analysis power design verification drive technology grid integrity frequency programming tcl perl automate efficiency cadence synopsys

Work Mode

On-site

Job Type

Full Time

Job Description

Job Requirements The responsibilities will include several of the following, but not be limited to: Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Closely working with Package team and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical activities of physical design during technology readiness, design & execution In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes Work Experience Experience Range:- 4Yrs - 10 Yrs Should be able to handle PD task independently and also should be able to manage the small team Should have experience in handling >1M instance count, 1 GHz frequency designs Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Show more Show less

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www.quest-global.com

Engineering Services

Beachwood

10,000+ Employees

581 Jobs

    Key People

  • Ajit Prabhu

    Chairman and CEO

  • Chandramouli Venkatesan

    Chief Operating Officer

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