PD Engineer

Job Requirements 3 to 6 years of exp in Hands on Chip top and Block level Timing closure. Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Multimode multi corner timing knowledge and timing closure at Top and Block level. Top level timing closure with sing off STA. Top level ECO implementation strategy development for netlist, RTL and timing level changes. Scripting experience in Perl/TCL Excellent debugging skills and ability to come up with creative solutions. Technologies from 28nm and below. Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Having proficiency with either PrimeTime, Tempus and Innovus is must Work Experience Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Performing floor-planning and routing studies and implementation at block and full-chip level Show more Show less