Layout Design Engineer

Company Description

Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered numerous RF and baseband applications in collaboration with Tier 1 and Tier 2 vendors.

Role Description

Analog Layout Engineer

Location: Noida/NCR, India

Experience: 2-4 Years

Qualification: B.E / B.Tech / M.Tech

Key Responsibilities:

• Perform

  full-custom layout

  of analog and mixed-signal circuit blocks such as PLLs, ADCs, DACs, LDOs, Bandgap references, and other analog IP.
• Work closely with circuit designers to understand design intent and optimize for performance, area, and yield.
• Implement layout in advanced process nodes including

  CMOS (e.g., 28nm, 16nm)

  and

  FinFET (e.g., 12nm, 8nm, 4nm)

  technologies.
• Conduct

  floorplanning

  , device matching, shielding, routing, and parasitic-aware layout for high-performance analog blocks.
• Perform

  DRC, LVS, ERC, and parasitic extraction (PEX)

  using industry-standard tools.
• Participate in

  design reviews

  and collaborate with cross-functional teams to meet project milestones and quality requirements.
• Apply

  layout best practices

  to minimize mismatch, noise, and electromigration issues.
• Ensure design robustness against

  process, voltage, and temperature (PVT)

  variations.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering or related field.

• 3+ years

  of experience in analog/mixed-signal layout in advanced

  CMOS and FinFET

  nodes.
• Strong knowledge of layout tools such as

  Cadence Virtuoso, Calibre, PVS

  , or equivalent.
• In-depth understanding of

  layout-dependent effects (LDE)

  , matching techniques, and analog layout optimization.
• Familiarity with

  EM/IR analysis

  ,

  antenna effects

  , and

  ESD layout guidelines

  .
• Experience working with

  high-speed

  and

  low-power

  analog design is a strong plus.
• Excellent communication and collaboration skills.

Preferred Skills:

• Experience with

  automated layout generation tools

  (e.g., SKILL, Tcl scripting).
• Knowledge of

  digital place & route flows

  and

  mixed-signal floorplanning

  .
• Experience with

  chip-level integration

  and

  top-level verification

  .