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Frontend RTL Design & Integration Engineer - ASIC/Timing Closure

310 years

0 Lacs

Hyderabad Telangana India

Posted:1 month ago| Platform: Linkedin logo

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Skills Required

design integration timing ip analyze constraints synthesis checks systemverilog triage reports verification automation development linting analysis test collaboration architecture security power scripting perl tcl data dma optimization

Work Mode

On-site

Job Type

Full Time

Job Description

We are Hiring : "Front-End RTL Design & Integration Engineers"

  • Location : Hyderabad
  • Experience Level : 310 years

Key Responsibilities

  • Understand RTL at structural level including IP boundaries and parameters.
  • Analyze and comprehend IP designs for integration.
  • Insert and validate assertions as needed.
  • Develop and manage design constraints for IP-level synthesis and timing.
  • Setup and maintain RTL build flows.
  • Perform IP quality checks across milestones :
  • Lint, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing)
  • Synthesis and Timing analysis
  • Waiver generation and management
  • Participate in subsystem-level IP integration.
  • Develop sample SystemVerilog testbenches to verify IP/block functionality.
  • Conduct initial triage and debug of functional issues.
  • Analyze and interpret quality reports and recommend RTL fixes.
  • Collaborate with verification teams to meet functional coverage and quality targets.
  • Ensure high-quality and on-time deliverables aligned with project milestones.
  • Contribute to design process automation and continuous improvement.

Preferred Skills & Experience

  • Solid understanding of ASIC development flows and RTL design methodologies.
  • Proficient in SystemVerilog for design and testbench with :
  • Multi-clock domain designs and constraint generation for STA.
  • Tools for linting, CDC/RDC analysis, synthesis, timing, waiver creation.
  • Familiar with industry-standard protocols like AXI/AMBA.
  • Capable of creating sanity test plans and running test cases.

Knowledge Of Front-end Integration Requirements And Collaboration With

  • Verification (coverage, test plan, debug)
  • Physical design (timing closure, reset/clock crossings, ECO handling)
  • Architecture, security, DFX, and power teams
  • Strong scripting skills in Perl, TCL, C-Shell, or equivalent.
  • Exposure to high-performance interfaces and data paths such as DMA, PCIe, and performance optimization techniques.
(ref:hirist.tech)

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