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FPGA Engineer - Static Timing Analysis

4 years

0 Lacs

hyderabad telangana india

Posted:4 days ago| Platform: Linkedin logo

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Skills Required

timing analysis electrical architecture design development verification xilinx test vivado resolve segmentation testing updating integration flow verilog programming scripting perl python linux debugging communication collaboration automation simulation

Work Mode

On-site

Job Type

Full Time

Job Description

Description

Job Title : FPGA Engineer (Architecture)Location : HyderabadExperience : 4+ YearsQualification : B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, or related field

About The Role

We are looking for a skilled FPGA Engineer (Architecture) with strong expertise in digital hardware design, FPGA development, and timing verification. The ideal candidate should have hands-on experience working with AMD (Xilinx) or Altera (Intel) FPGA platforms, and the ability to handle complete design-to-verification responsibilities independently or as part of a team.

Key Responsibilities

  • Design, implement, test, integrate, and deliver system-level digital designs for FPGA-based solutions.
  • Perform architecture design and timing verification for FPGA blocks.
  • Execute static timing analysis (STA) using tools such as Vivado and ensure design closure.
  • Debug and resolve timing-related issues across multiple FPGA families.
  • Perform manifold segmentation and partitioning of complex FPGA designs.
  • Run and maintain internal scripts for performance testing, updating them as required.
  • Ensure timely completion of design and verification tasks within project schedules.
  • Collaborate closely with cross-functional teams for system integration and validation.
  • Work effectively both independently and within a team-oriented environment.

Required Skills & Expertise

  • Strong knowledge of FPGA design flow and timing verification.
  • Hands-on experience with FPGA platforms such as AMD (Xilinx) and/or Altera (Intel).
  • Proficiency in Verilog for digital hardware design.
  • Basic understanding of Static Timing Analysis (STA) and familiarity with Vivado or similar tools.
  • Good programming/scripting experience in Perl, Python, and Tcl.
  • Working knowledge of Linux-based environments.
  • Excellent problem-solving and debugging skills.
  • Strong communication and collaboration abilities.

Preferred Qualifications

  • Experience with system-level FPGA architecture design and timing optimization.
  • Exposure to performance analysis and test automation frameworks.
  • Familiarity with simulation and verification tools.
(ref:hirist.tech)

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