DV Engineer 2

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Design Verification Engineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISiE) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond

• Required/Minimum Qualifications
• Bachelor's Degree in Electronics Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
• OR Master's Degree in Electronics Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
• OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• OR equivalent experience.
• 4+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals
• 2+ years of debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• 2+ years experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM)
• 2+ years experience with scripting language such as Python or Perl or shell scripts.

Additional or Preferred Qualifications

• 5+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental

• In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments

• Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar

• Knowledge of System Verilog class, constraints, coverage and assertions.

• Experience in scripting languages such as Python or Perl

• Hands-on experience in Formal property verification, formal verification of computational data path designs

Desirable:

• Hands on experience in Formal property verification

#SCHIEINDIA

• Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

• Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification.

• Create test-plans and write tests to provide complete features coverage.

• Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.

• Triage and debug testbench, simulation, and emulation fails.

• Develop Makefiles and scripts for verification infrastructure.

• Agile development methodologies including code reviews, sprint planning, and frequent deployment.

• Collaborate with teams across sites and geographies.