Digital Design Front End

OUR STORY

At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today.

When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world!

Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.

Job Description:

As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets.

Responsibilities

• Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications.
• Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets.
• Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains.
• Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA).
• Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects.
• Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash.
• Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery.
• Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration.
• Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
• Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency.
• Mentor junior engineers, and provide technical leadership and guidance across multiple design projects.
• Contribute to the innovation quotient of the team via Patents, Industry standard publications etc.

Qualifications:

• Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience.
• Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture.
• Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems.
• Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
• Familiarity with formal verification techniques, static/dynamic power checks.
• Proficiency in scripting and automation using Python.
• Excellent leadership, communication skills.
• Experience working with global cross-functional teams.
• Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus.

Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future!

To discover more, visit st.com/careers