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Design Verification Engineer | UVM SystemVerilog

Design Verification Engineer | UVM SystemVerilog

Coventine Digital

3 - 8 years

6 - 14 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

Design Verification PCIe UVM GLS SystemVerilog CDC Gate-Level Simulation Protocol Verification RTL Simulation DDR Assertion-Based Verification Functional Verification SoC Verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

multiple Design Verification (DV) Engineers

Open Positions

1. DV Engineer GLS / UVM / SystemVerilog / CDC

Experience
: 3–8 years
Skills
: Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification

2. DV Engineer – PCIe / DDR / UVM / SV

Experience
: 4–18 years
Skills
: Protocol-level verification, PCIe or DDR, UVM, SystemVerilog

3. DV Engineer – UVM / SystemVerilog

Experience
: 5–10 years
Skills
: Testbench architecture, functional verification, scalable UVM environments

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Design Verification Engineer | UVM SystemVerilog

Experience & Salary

Skills Required

Work Mode

Job Type

Job Description

multiple Design Verification (DV) Engineers

Open Positions

1. DV Engineer GLS / UVM / SystemVerilog / CDC

Experience

Skills

2. DV Engineer – PCIe / DDR / UVM / SV

Experience

Skills

3. DV Engineer – UVM / SystemVerilog

Experience

Skills

More Jobs at Coventine Digital