2 Assertion-Based Verification Jobs

What You'll Be Doing: Leading and mentoring a team of formal verification engineers to ensure high-quality IP delivery. Developing and driving formal verification plans, aligning with project timelines and IP deliverables. Defining test plans tailored to high-complexity digital IPs such as UFS MIPI Unipro I3C, AMBA, and other interconnect protocols. Identifying and implementing state-of-the-art formal verification methodologies and tools, including assertions, SystemVerilog Assertions (SVA), and custom verification environments. Driving innovation to enhance verification efficiency and coverage. Evaluating and mitigating verification risks early in the design phase to ensure IPs meet high-quality standards. The Impact You Will Have: Ensuring the robustness and quality of our digital design hardware IPs. Delivering best-in-class, verified IPs to semiconductor design companies globally. Enhancing verification efficiency and coverage through innovative methodologies. Mitigating verification risks early in the design phase, ensuring timely and high-quality IP releases. Contributing to the development of high-performance silicon chips and software content. Driving continuous technological innovation in chip design and verification. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Advanced degrees preferred. 2 6 years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs. Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance. Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal. Extensive experience in digital design and verification for high-speed interconnect protocols. Who You Are: An excellent problem solver with a proactive approach to identifying and addressing verification challenges. A collaborative team player who thrives in a dynamic environment. An effective communicator who can lead and mentor junior engineers. An innovative thinker who drives continuous improvement in verification methodologies. A detail-oriented professional committed to delivering high-quality IPs.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: As an ideal candidate, you are a seasoned professional with a passion for innovation and a deep understanding of ASIC design and verification You have a proven track record in developing high-level verification environments using System Verilog/UVM and possess a keen eye for detail Your expertise in memory interface protocols like DDR and LPDDR sets you apart, and you excel in debugging and problem-solving skills You are self-motivated and possess excellent communication skills, enabling you to work seamlessly within global teams Your leadership abilities allow you to guide technical teams and enhance verification strategies and test environments, ensuring high-quality deliverables, What Youll Be Doing: Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores, Perform verification tasks for IP cores, working closely with RTL designers, Drive ownership of critical areas of verification along with a team of talented verification engineers, Develop and implement advanced test plans and test environments at both unit and system levels, Code and debug test cases, implementing complex checkers and assertions, Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met, Manage regressions and contribute to the continuous improvement of verification strategies and test environments, The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores, Contribute to the development of cutting-edge technologies that power the Era of Smart Everything, Enable the creation of high-performance silicon chips and software content, driving innovation in various industries, Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning, Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security, What Youll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience, Proven experience in developing HVL (System Verilog/UVM) based test environments, Expertise in developing and implementing test plans, checkers, and assertions, Proficiency in extracting verification metrics such as functional coverage and code coverage, Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes, Who You Are: You are a detail-oriented, self-motivated individual with strong problem-solving skills Your excellent communication skills enable you to work effectively within global teams You possess deep knowledge of HDLs such as Verilog and scripting languages like shell/Perl/Python, and you thrive in a project and team-oriented environment, The Team Youll Be A Part Of: You will be part of the DesignWare IP Verification R&D team at Synopsys, working closely with RTL designers and a global team of experienced verification engineers This team focuses on developing state-of-the-art verification environments for synthesizable cores, contributing to the success of Synopsys Design & Verification domain, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process