13 Rtl Simulation Jobs

As a SOC Performance Modeling Engineer at AMD, you will be an integral part of the Client Performance Modeling Team based in Hyderabad, India. Your primary responsibility will involve analyzing the architectural performance of notebook and desktop processors through modeling and RTL simulation. By collaborating with SoC, IP & Model architects, you will evaluate and debug CPU/GFX/NPU processor performance and suggest architectural enhancements to drive innovation. To excel in this role, you should possess a deep passion for cutting-edge SoC architecture, digital design, and verification. Your effective communication skills and ability to work seamlessly with architects & engineers across different locations and time zones will be crucial. Strong analytical and problem-solving abilities are essential, coupled with a willingness to learn and tackle challenges head-on. Key responsibilities in this role include developing architectural models, tools, and infrastructure, optimizing performance features, proposing enhancements for next-gen SOCs, conducting trade-off studies for performance, power, and area, evaluating benchmarks for various processors, advancing simulation infrastructure and methodology, and providing technical guidance to the Client SoC team. The ideal candidate would have 3-15 years of industry/academic experience, expertise in computer system simulation and performance evaluation, familiarity with ASIC HW design and verification languages/tools such as Verilog, System Verilog, System C, OVM/OVC, proficiency in programming and scripting languages like C/C++, Perl, Python, and a track record of analyzing system bottlenecks to optimize computing systems for performance. Additionally, detailed microarchitecture knowledge of CPU, GPU, NPU, I/O subsystem, and/or DRAM controller would be advantageous. An academic background in Computer/Electrical Engineering with a Bachelor's or Master's degree is required to qualify for this position at AMD. Explore the AMD benefits at a glance to discover the comprehensive perks offered to our valued employees.,

The culture at our organization is defined by the people who contribute to it. We foster a culture of passion for technology solutions that have a tangible impact on businesses. Additionally, we prioritize the pursuit of individual passions by our team members. Collaborating with us offers you the opportunity to gain a deep understanding of various industries and cutting-edge technologies. This knowledge enables us to develop forward-thinking and impactful solutions. Moreover, being a part of MarvyLogic can facilitate personal growth, leading you towards a more enriching and fulfilling life. To be considered for this role, you should possess the following qualifications: - A minimum of 10 years of experience in FPGA Design and Debug, preferably working with Xilinx Ultrascale+ and Virtex7 - Proficiency in utilizing tools such as Xilinx Vivado/Coregen/Synplify and developing/maintaining Timing/IO constraints (UCF) - Experience with managing multiple high-speed clock domains and integrating third-party IP onto Xilinx transceivers - Familiarity with working on FMC daughter-cards, High-Speed Cables/Connectors, etc. - Extensive debugging experience using Xilinx ILA, Protocol Analyzers, Oscilloscope, Logic Analyzers, etc. - Proficiency in PERL/TCL scripting and database management between FPGA and ASIC RTL - Knowledge of front-end RTL tools such as RTL Simulation, Synthesis, DFT, Timing - Ability to modify/adapt RTL designs for FPGA implementation and optimize designs to achieve FPGA area/performance goals - Collaboration with DV and Firmware/Software teams throughout the validation process, including post-silicon bring-up Your responsibilities in this role will include: - Effectively collaborating and communicating with multi-site teams - Reviewing FPGA netlist releases (block/chip) and overseeing ASIC product life cycle stages, including requirements, design, implementation, testing, and post-silicon validation If you meet the specified qualifications and are ready to take on these responsibilities, we welcome you to apply for this challenging and rewarding opportunity.,

NVIDIA is a company that has continually reinvented itself, with a rich history that includes inventing the GPU, which transformed the PC gaming market and modern computer graphics. The company has also played a pivotal role in revolutionizing parallel computing. Today, the field of artificial intelligence is experiencing rapid growth globally, necessitating highly scalable and massively parallel computation power, an area in which NVIDIA GPUs excel. NVIDIA is committed to evolving and adapting to new challenges that are unique, complex, and impactful on a global scale. The company's mission is to enhance human creativity and intelligence, making a lasting impact on the world. Joining NVIDIA means becoming part of a diverse and supportive environment where individuals are encouraged to strive for excellence in their work. As an NVIDIAN, you will have the opportunity to work with a team that is dedicated to designing, implementing, and debugging the next generation of GPUs, SOCs, and system simulation environments. Your role will involve developing the core verification infrastructure for a full-system platform used in the development of discrete graphics and computing chips. This will entail utilizing object-oriented C++ and System-C simulation infrastructure to model and verify some of the world's largest chips through a distributed-computing-based execution and triage environment. As a member of our team, you will be responsible for creating environments to model and simulate future GPU and SoC systems, integrating features well before they are physically built or implemented in driver software. You will collaborate with architecture and engineering teams to optimize the functionality and performance of upcoming NVIDIA chips. Our team is involved in every stage of chip development, from architectural specification to verification and production. To be successful in this role, you should hold a Bachelor's or Master's degree in computer science/computer engineering or possess equivalent experience. Additionally, you should have at least 4 years of experience in professional object-oriented C++ programming and System-C simulation/modeling. Familiarity with Transaction Level Modeling and Verilog/System Verilog is advantageous, as is experience in RTL simulation. Knowledge of software development lifecycle on Linux-based platforms and an understanding of computer and memory system architecture are preferred. Strong communication skills are essential, as you will collaborate with colleagues from diverse backgrounds on a regular basis. NVIDIA offers competitive salaries and a comprehensive benefits package. The company is home to some of the most talented and hard-working individuals globally, and due to rapid growth, our engineering teams are expanding. If you are a creative, autonomous engineer with a genuine passion for technology, we invite you to join our diverse, international, and fast-paced team at NVIDIA and contribute to the development of next-generation products adhering to the highest production-quality standards.,

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity andforward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers. What You ll Be Doing: Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity andmanufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on newtools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You ll Need: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency inindustry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, andmethodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Who You Are: Excellentproblem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Makefiles), Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Make, Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies Proficiency in scripting (Python, Bash, Makefiles), Linux system administration, and version control tools (Git, Mercurial) is essential Experience in ASIC flows and standard CAD tools is required Immediate joiners with a notice period of 15 days or less are preferred