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Design and Verification Engineer

7 - 12 years

20 - 35 Lacs

Posted:2 days ago| Platform: Naukri logo

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Work Mode

Hybrid

Job Type

Full Time

Job Description

Must Have:
SV/UVM Test Bentch Development Any Protocols:

  • (PCI Express or UCIe, CXL or NVM
    • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

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Information Technology & Services

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