Posted:1 day ago|
Platform:
Hybrid
Full Time
Core Requirements
Basic understanding of CMOS and gate level circuit designsFamiliarity with SPICEFamiliarity with Verilog simulationsGood communication skills and ability to work well in a team
Preferred Qualities
Analytical capability for complex gate level circuit designsExperience in SystemVerilog, PLI codingExperience in UVM Test BenchExperience in DRAM, SRAM or other memory related fieldsExperience in AMS verification and co-simExperience Level 5+ years
Acesoft Labs
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