Design and Verification Engineer

SISOC Semiconductor

4 - 9 years

20 - 35 Lacs

Noida Hyderabad Bengaluru

Posted:1 month ago| Platform:

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Skills Required

ASIC Verification Ddr USB Verilog Ethernet SOC Verification PCIE System Verilog UVM Ip Verification GLS

Work Mode

Hybrid

Job Type

Full Time

Job Description

Job Summary:

Senior Design Verification Engineer

Key Responsibilities:

Develop and execute comprehensive
test plans
based on design specifications and architectural documents.
Build and maintain
constrained-random verification environments
using
SystemVerilog UVM
.
Write
testbenches, test cases
, and functional coverage to ensure design quality.
Debug RTL and testbench issues using industry-standard tools (e.g., VCS, ModelSim, Verdi, DVE).
Develop and track
coverage metrics
(code, functional, and assertion coverage).
Contribute to the
automation of the verification process
(e.g., regression tools, continuous integration).
Participate in design and verification
reviews
and provide technical guidance to junior engineers.

Required Skills & Experience:

Bachelors or Masters degree in
Electronics, Electrical Engineering, or Computer Engineering
.
3Years to 25 Years
of experience in
RTL verification
of complex digital designs.
Proficiency in
SystemVerilog
,
UVM methodology
, assertions, and functional coverage.
Strong debugging and problem-solving skills.
Experience with
simulation tools
(Synopsys VCS, Cadence Incisive/Xcelium, ModelSim, etc.).
Solid understanding of
SoC architecture, AMBA protocols
(AXI, AHB, APB).
Hands-on experience with
scripting
(Python, Perl, Tcl, or Shell).
Familiarity with
version control systems
(e.g., Git, Perforce).

Preferred Qualifications:

Exposure to
PCIe, Ethernet, USB, DDR
,
Jtag
or other high-speed interfaces.

Why Join Us:

Work on cutting-edge technology with top-tier semiconductor clients.
Opportunity to lead verification activities and mentor junior team members.
Competitive compensation and flexible work culture.

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