Soc Verification Engineer

2 - 7 years

0 - 1 Lacs

Posted:2 days ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • Core Technical Skills

    :
    • SystemVerilog / UVM testbench and coverage methodologies
    • Constraint-random verification, simulation and debug flow
    • Formal verification techniques (e.g. Jasper, VC Formal)
    • Scripting languages: Python, TCL, Perl, Shell
    • Experience with high-speed protocols (PCIe, DDR, Ethernet) and emulation tools
  • Resume & Interview Prep Advice

    :
    • Highlight projects involving ASIC/SoC verification, testbench implementation, coverage closure using UVM/SystemVerilog Reddit+15Reddit+15Meta Careers+15Indeed+8Atos Jobs+8Indeed+8Reddit+1Indeed+1Reddit+2Meta Careers+2Reddit+2Reddit+2Reddit+2Reddit+2
    • Showcase contributions in debugging RTL, developing functional coverage models, and scripting automation for regressions

Role & responsibilities

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