Role Greetings from Sivaltech!! Hope you are doing great!!!! We have an exciting job opportunity for Lead Design Verification Engineer in Sivaltech for both Bangalore and Hyderabad locations. Please find below the detailed Job Description and Company Profile as well. • Working experience in IP / SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Sivaltech is a product engineering company with expertise in silicon design and software development. Our head office is in Milpitas, California, U.S.A. with branches in India at Bengaluru and Hyderabad& responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.
• Working experience in IP/ASIC/ SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Role & responsibilities Preferred candidate profile
Bachelor's degree with 5+ years of experience, Computer Engineering, or Electronic/Electrical Engineering. Demonstrated experience in ASIC design verification methodologies and flows. Develop detailed and comprehensive test plans. Develop verification test benches in SV/UVM at block, inter-block, and chip levels. Apply innovative verification techniques including assertions to Mix Signal designs. Participate in the review of design verification coding and coverage metrics. Work collaboratively with the team to develop & incorporate the latest test technologies & processes. Preferred experience of System Verilog Models for the Analog blocks. Understanding of adding connect module at the interaction of schematic and model while running AMS simulations. Role & responsibilities Preferred candidate profile
Technologies from 28nm, 20nm, 14nm, 10nm, 7 nm. Block level floorplanning, power planning and IR drop analysis. Timing closure Multimode multi corner optimization and closure. Clock tree synthesis and advanced clock tree implementation. Block level timing closure with sign off STA . Block level ECO implementation involving netlist level logical changes. Library performance analysis and fine tuning for implementation. Excellent debugging skills in implementation issues and ability to come up with creative solutions.
Role & responsibilities Those who had a chance to work on CPU, GPU and / or NPU would be better on 3 or 5 nm Technology . Experience Levels would 4-8 years.
IoT/Wearables embedded systems engineers will be a part of a team of developers with expertise in low-level device driver software and HW/SW interfaces The candidates are proficient in C, and JTAG based hardware debugger (preferably Lauterbach usage) knowledge is required These candidates will need a very good understanding of ARMv7/ARMv8/x86 architectures and will need to know how to utilize off-target development and debugging platforms in-addition to on target development Strong familiarity and understanding of Operating System internals, RTOS Internals and Linux Internals is very useful These candidates will work with minimal supervision, perform task definition, and work breakdown including time estimation as well as create, document and execute detailed test plans These candidates will work closely with hardware design engineers to successfully drive projects to completion Qualification Requirements : 2 - 6 years of development and test experience in embedded software and firmware Experience in RTOS and Linux internals Experience in ARM/x86 internals Good working experience in using IAR/Keil development environment Good experience in C programming Education Requirements: Required : Bachelors in Computer Engineering, Computer Science and / or Electrical Engineering Preferred : Masters in Computer Engineering, Computer Science and / or Electrical Engineering
Understanding the business requirements from Sivaltech clients and defining the scope and key objectives of Sivaltech IP- 20% : Collaborating with Sivaltech clients and other stake holders in order to understand the business background and clearly define the scope and key objectives of the project. Developing clear statement of objectives and performance metrics. Translating Sivaltech client needs in to business requirements into detailed analytical requirements in accordance with petitioner s problem-solving approach. Creating hypotheses of variable relationships relevant to that business problem. Designing the complete Architectural Framework and spec for future versions of the IP - 20% : Discussing the merits and demerits of various alternative analytical approaches and with respective to Sivaltech client needs. Working with the client to finalize intermediate, final deliverables, and the timelines for the project. Interacting with RTL Design, Verification and physical design teams inhouse to make and create sustainability report and defining achievable standards along with trade offs to meet the defined spec. Extracting relevant data from appropriate data sources for the execution of the project. Program Management - 25% : Data quality check - Ensuring data integrity by cross - checking the extracted data with the relevant stakeholders for data accuracy and consistency. Maintaining an accurate check on Open source vs indigenously developed components for the IP while not breaching the open source standards and agreements. The cndidate will work in conjunction with other team members to develop Business Process environments specification documents and modify high-level architecture of the IP. Sync Ups with RTL design team members and regular cross verification of the architecture document with simulation environment. Improving Sivaltech verification signoff process on a continuous basis for reusability and smooth handover to Physical design team by continuously tracking the methodology standards and updating the sign off methodology. Managing the overall schedule and incorporating inputs from marketing teams. Meeting clients and architecting variants of the IP- 35% : Candidate will travel extensively meeting clients to establish business cases for Sivaltech IP variants with different foundries and technology nodes. With sound understating of the ASIC business in US, candidate will be responsible for architecting different variants of the IP while understanding client specifications and will be responsible for embedding the same in architecture document. Will be responsible for feasibility analysis and clearly define the standards and variants of the VIPs that needs to be developed. Collating and presenting the recommendations and insights that would enable continuous measurable improvement in the client s business decisions. Preparing executive summary of the results for the senior management. The position of Programmer Analyst is a professional and specialized occupation which requires, at a minimum, a Bachelor s Degree in Computer Science, Computer Applications, CIS, Information Technology or related.
The ideal candidate will have experience in managing a project from start to finish. You will be able to create a plan of action that considers a fixed timeline and evaluate risks. Additionally, you should have experience in managing people and be an effective communicator. Responsibilities - Direct and oversee the completion of the project - Develop a plan of action including schedule, resources, and work plan - Assess risks and establish contingency plans - Manage work and inputs from a variety of stakeholders Qualifications - Bachelor's degree - 4+ years of experience in project management or relevant fields - Demonstrated ability to deliver a completed project - Strong communication skills - Experience working with a team,
SoC level verification using C + UVM based test cases Good debugging skills at SoC level using tarmac / waveform UVM bench debug - Experience in working with cadence simulator and simvision - Experience in peripherals SPI / I2C / I3C / CAN and LIN is a plus
he engineer should be well-versed in Verilog/VHDL RTL coding and experienced in using Mentor DfT tools and Cadence tools. Key requirements include: Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Role & responsibilities Preferred candidate profile
Role & responsibilities - Good knowledge on ARM M core operations and able to write code in C for ARM processor - Expert in UVM bench – able to adapt quickly to existing bench and start creating test cases - Experience in using Cadence and Synopsys VIP - Debugging test case using disassembly and tarmac for ARM cores - AHB and APB interface protocol - Expert level knowledge in DMA / Interrupt handling / Cache / interconnect - Good debugging skills at SoC level using tarmac / waveform – UVM bench debug - Experience in working with cadence simulator and simvision - Experience in peripherals SPI / I2C / I3C / CAN and LIN is a plus Preferred candidate profile Immediate joining
Role & responsibilities • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Preferred candidate profile Immediate joining