Dft Design Engineer

5 - 8 years

20 - 27 Lacs

Posted:None| Platform: Naukri logo

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Job Type

Full Time

Job Description

he engineer should be well-versed in Verilog/VHDL RTL coding and experienced in using Mentor DfT tools and Cadence tools.

Key requirements include:

  • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis
  • Proficiency in simulation debug with timing/SDF
  • Experience with LBIST and Mixed Signal Radar ICs is highly desirable
  • Ability to debug and root cause simulation failures
  • Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment

    Role & responsibilities

Preferred candidate profile

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