291 Chip Design Jobs - Page 5

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. At Arm, our work goes beyond multiple divisions where we'drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

Assist in the design, development, testing, and deployment of software applications. Write clean, maintainable, and efficient code using languages such as C#, Java, Python, or C++ . Collaborate with senior engineers and team members to understand project requirements and deliver solutions. Participate in code reviews and incorporate feedback to improve code quality. Debug and troubleshoot software issues under the guidance of more experienced developers. Contribute to documentation and support the maintenance of existing systems. Learn and apply best practices in software engineering, including version control, testing, and agile methodologies. Qualifications: bachelors degree in Computer Science, Software Engineering, or a related field. 1 year of hands-on experience in software development (internships or co-op experience may be considered). Familiarity with object-oriented programming and basic understanding of data structures and algorithms. Exposure to development tools such as Git, IDEs, and debugging tools. Strong problem-solving skills and a willingness to learn. Good communication and teamwork abilities. Minimum Qualifications Masters Level Degree and 0 years related work experience; Bachelors Level Degree and related work experience of 2 years

The SFS-ADE division has developed two network-centric products focused on advanced data management and fleet-level applications. Designed to strengthen customer retention and sharpen competitive differentiation, both products are fully managed from India with end-to-end PLC ownership. They have achieved widespread adoption across wafer and IC fabrication facilities. Responsibilities: Team Leadership & Mentorship : Lead and mentor a team of software engineers, fostering a culture of technical excellence, collaboration, and continuous learning. Product & Technology Ownership : Drive the product and technology roadmaps, innovation strategy, and customer engagement for SFS-ADE s network products FabVision and SurfServer . Platform Vision : Envision server products as scalable data platforms, enabling actionable insights through advanced analytics and AI integration. Lifecycle Stewardship : Serve as the software stakeholder in the Product Life Cycle (PLC) group, ensuring alignment across development stages. Cross-Functional Collaboration : Partner with customers and internal KLA product groups to co-develop fleet-level solutions and accelerate product adoption. Use Case Development : Define and evolve use cases that enhance product relevance, customer value, and long-term stickiness. Project Execution : Oversee planning, prioritization, and execution of software projects, ensuring timely delivery and quality outcomes. Talent Development : Champion team growth through coaching, skill development, and succession planning. Technology Foresight : Stay current with advancements in cloud architecture and data-driven decision-making, applying them to elevate product capabilities. Process Optimization : Lead continuous improvement initiatives across development processes, tools, and engineering methodologies. Qualifications: bachelors or masters degree in Computer Science, Engineering, or a related field. Demonstrated experience in building software products and driving successful customer adoption. Strong understanding of cloud infrastructure, centralized server systems, and data center solutions. Proven leadership and team management capabilities, with a track record of guiding high-performing engineering teams. Proficiency in programming languages such as C++, C#, Angular, and Java. Excellent analytical and problem-solving skills, with a solution-oriented mindset. Strong communication and interpersonal skills, with the ability to collaborate effectively across teams and stakeholders. Minimum Qualifications Bachelors degree plus 12 + years of experience OR Masters degree plus 8 + years of experience

You are a visionary leader with a deep understanding of Compensation and Benefits (C&B) strategies and their alignment with business goals. You thrive in dynamic environments and have a proven track record of designing and executing complex Total Rewards programs that drive employee engagement and organizational success. You are passionate about innovation and thought leadership in the HR space, and you excel at building systems and frameworks that deliver measurable outcomes. Your expertise spans across varied compensation plans, long-term grants, and benefits design. You are adept at setting the vision and strategy for C&B functions, ensuring alignment with talent acquisition and performance management systems. You are a strategic thinker who can link compensation frameworks to broader business strategies, and you are comfortable representing the organization in external HR forums as a speaker and thought leader. You are collaborative, detail-oriented, and results-driven, with exceptional communication skills that allow you to influence and inspire stakeholders at all levels. You are ready to lead a team and make a significant impact on Synopsys Total Rewards strategy. What you'll Be Doing: - Setting the vision and strategy for the Compensation & Benefits (C&B) function, ensuring alignment with organizational goals. - Leading the Total Rewards function, including deferred compensation plans, non-executive compensation plans, long-term grants, and benefits design. - Designing and executing outcome-based health and we'llness programs that enhance employee we'll-being. - Directing complex C&B programs and projects, ensuring successful implementation and measurable results. - Driving thought leadership and innovation in Total Rewards, positioning Synopsys as a leader in the HR space. - Representing Synopsys in external C&B and HR forums as a speaker and key contributor. - Collaborating with cross-functional teams to align compensation frameworks with talent acquisition and performance management systems. - Setting up HR systems and processes that integrate business perspectives and deliver strategic value. The Impact You Will Have: - Shape Synopsys Total Rewards strategy to attract, retain, and motivate top talent. - Enhance employee engagement and satisfaction through innovative compensation and benefits programs. - Drive alignment between compensation frameworks and business strategies, ensuring organizational success. - Position Synopsys as a thought leader in the HR space through external representation and contributions. - Improve health and we'llness outcomes for employees through strategic program design. - Build robust HR systems and processes that support long-term organizational growth. - Foster a culture of innovation and excellence within the Total Rewards function. - Influence key stakeholders and drive strategic decision-making across the organization. What you'll Need: - Extensive experience in Compensation & Benefits, including deferred compensation plans, long-term grants, and benefits design. - Proven ability to set vision and strategy for Total Rewards functions. - Expertise in aligning compensation frameworks with talent acquisition and performance management systems. - Strong project management skills, with experience directing complex C&B programs and initiatives. - Thought leadership and innovation in the HR space, with a track record of external contributions. Who You Are: - A strategic thinker with a deep understanding of business and HR alignment. - A collaborative leader who excels at building relationships and influencing stakeholders. - Detail-oriented and results-driven, with a focus on delivering measurable outcomes. - An excellent communicator, both written and verbal, with the ability to inspire and influence. - Passionate about innovation and continuous improvement in the HR space. The Team you'll Be A Part Of: You will lead the Regional Compensation & Benefits team, reporting to the Global Compensation and Benefits leaders. This team is focused on driving Synopsys Total Rewards strategy, ensuring alignment with business goals, and delivering innovative programs that enhance employee engagement and organizational success.

You will be involved in the post-silicon characterization and production testing of automotive System-on-Chip (SoC) products. These products are based on ARM or RISC-V microcontrollers, with a primary focus on digital IP and functional blocks. The role encompasses a broad range of tasks, including analyzing device performance, ensuring compliance with datasheet specifications, and developing production test programs for automotive microcontrollers. In your new role you will: Responsible for Post Silicon Characterization/Production Test of ARM or RISC-V based micro-controller Automotive SoC products, with main focus on Digital IP/Functional Blocks. Perform characterization to analyze device performance and compliance to datasheet specification. Develop Production Test program for Automotive microcontrollers. Conceptualize, design and implement hardware and automation software for characterization of Automotive SOCs. Work closely with chip design team to debug silicon issues. Demonstrate technical innovation in measurement automation on ATE(V93K preferable) and bench (LabVIEW) platforms. Your Profile You are best equipped for this task if you have: MTech/M.E/MS or B-Tech/B.E in any of the specializations related to the field of Electronics / Microelectronics / VLSI. Strong Electrical Circuits Fundamentals. Strong troubleshooting & problem solving ability. Good Firmware coding & scripting skill. Experience in using equipment like Oscilloscopes, Source Measure Units, Power Supplies, Functional Generators etc is a plus. Experience in automating characterization using an ATE or NI LabVIEWis a plus

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

Key Responsibilities: Perform block- and chip-level functional verification of complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs and subsystems. Create and execute detailed verification test plans based on specifications. Develop constrained-random and directed test cases and debug simulation issues. Conduct functional and code coverage analysis and drive coverage closure. Use RAL (Register Abstraction Layer) for register-level testing. Develop and validate SystemVerilog Assertions (SVA). Candidate Requirements: • Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. • Experience: 6–10 years of relevant experience in ASIC/SoC design verification.

The IBM Z Hardware Product Management team is responsible for bringing to market IBMs flagship mainframe products. We are currently seeking an experienced candidate to fill the role of the Product Operations specialist on the System Infrastructure 3 in a box team. The product operations specialist will be responsible for driving the team to meet the following objectives: Understanding industry trends and market needs and condensing these into product requirements. Defining a clear, executable roadmap that aligns with the overall IBM Z strategy and specific program objectives. Articulating technical and business value for both IBM and our clients Working with Subject Matter Experts to create marketing, and sales enablement collateral Setting key success factors and driving to these metrics Working with clients through sponsor userships, briefings or direct interactions for insights, feedback and validation of strategic direction Assess product performance in market spanning customer experience, pipeline health and market share to update portfolio management, offering/product design, and GTM and delivery approach (including sun-setting). Responsible for defining business governance framework (key metrics etc.) and tracking all metrics to ensure the health of the business, this includes pipeline analysis, win/loss analysis, operational analysis, and customer analytics. Required education Bachelor's Degree Required technical and professional expertise The candidate should possess strong project management skiils (coordinating activities across the team members, monitoring and communicating progress against the key success factors and business metrics). Direct experience with, or the familiarity of the processes of at least one of the following: System design/development: Chip design, development, fabrication Networking LAN/WAN/SAN Datacenter practices Proficiency with AHA, Microsoft office, Monday, Slack

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-EDA #LI-Hybrid

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

People Operations, Associate Bengaluru, Karnataka, India Apply Now Save Category: People Hire Type: Employee Job ID 10255 Date posted 06/11/2025 Share this job Email LinkedIn X Facebook We Are: You Are: You are a proactive and detail-oriented individual with a passion for People Operations. With 0 - 2 years of experience in HR operations, you have a solid foundation in managing the employee lifecycle from pre-onboarding through offboarding. Your experience with HRIS systems, ServiceNow, particularly SuccessFactors or similar tools, equips you with the skills to handle complex employee data and processes. You hold a BA/BS degree and have honed your ability to manage multiple tasks and deadlines with exceptional organizational skills. Your strong stakeholder partnering skills enable you to collaborate effectively with various teams, ensuring the delivery of impactful HR solutions. You are familiar with Microsoft Office and project management tools, and your excellent written and spoken communication skills make you a reliable and clear communicator. Your resourceful problem-solving abilities allow you to troubleshoot issues independently and drive meaningful solutions. What You ll Be Doing: Collaborate effectively with stakeholders to proactively determine and deliver relevant and impactful People (HR) operation solutions to business and system challenges. - Accurately perform employee lifecycle transactions/processes, including onboarding, offboarding, transfers/job status changes, timekeeping, time off and leave, extended workforce, and other responsibilities as assigned. - Recommend and draft employee lifecycle processes and procedures that enhance and optimize existing HR practices, ensuring they remain fit for purpose and benefit stakeholder teams. - Be a trusted resource for People (HR) systems, data, and process knowledge to interpret and analyze processes. - Drive People operation enhancements by supporting new module roll-out and optimization initiatives. - Manage requests, workflows, and develop a knowledge base and reporting metrics using ServiceNow. The Impact You Will Have: Streamline HR processes to improve efficiency and accuracy in employee lifecycle management. - Enhance stakeholder satisfaction by delivering timely and effective HR solutions. - Contribute to the optimization of HR practices, ensuring they are aligned with organizational goals. - Support the successful rollout and adoption of new HR modules and tools. - Provide valuable insights and data analysis to drive informed decision-making in HR operations. - Foster a collaborative and supportive HR environment, building trust with stakeholders and team members. What You ll Need: 0 - 2 years of People (HR) operations related APAC work experience. - BA/BS degree. - Experience with HRIS administration, particularly SuccessFactors or similar tools. - Knowledge of managing requests, workflows, developing knowledgebase, and reporting metrics using ServiceNow. - Exceptional organizational skills and attention to detail. - Proficiency in Microsoft Office suite and familiarity with project management tools. - Excellent written and spoken communication skills. Who You Are: Detail-oriented and organized. - Resourceful problem-solver. - Effective communicator. - Collaborative team player. - Proactive and initiative-driven. The Team You ll Be A Part Of: You will be part of a dynamic People Operations team focused on delivering exceptional HR services and solutions. Our team collaborates closely with various stakeholders to ensure smooth HR operations and continuous improvement of HR processes. We value innovation, teamwork, and a commitment to excellence in all our endeavors. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs ASIC Digital Design, Architect Bengaluru, India Engineering Senior Software Engineer (R&D Engineering) Yerevan, Armenia Engineering R&D Engineering, Staff Engineer - Design Verification/ VIP Verification Engineers Noida, India Engineering

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job Description Category Engineering Hire Type Employee Job ID 9978 Remote Eligible No Date Posted 19/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Analog Design Engineer with a strong passion for innovation and technology. With a solid background in analog design fundamentals and device physics, you excel at developing high-speed IO designs in advanced technologies. Your expertise in memory interface PHY IPs (DDR/HBM/UCIe) and your familiarity with JEDEC requirements position you as a valuable asset in our team. You are adept at collaborating with cross-functional teams, driving innovation, and ensuring the delivery of high-quality products. Your excellent written, verbal communication, and interpersonal skills enable you to effectively convey complex technical concepts and work seamlessly with colleagues across the globe. You thrive in a dynamic environment where you can leverage your skills to make a significant impact on the development of next-generation technologies. What You'll Be Doing: Leading the development of next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe). Driving innovation towards high-speed IO designs for memory interface PHY IP in CMOS/FinFET/GAA. Collaborating with cross-functional teams across the globe to ensure seamless project execution. Ensuring compliance with JEDEC requirements for memory interfaces and standards. Implementing and validating ESD and reliability concepts in design processes. Focusing on signal integrity and power integrity to enhance product performance. The Impact You Will Have: Accelerating the development and integration of high-speed memory interface PHY IPs. Enhancing the performance and reliability of our silicon IP portfolio. Driving innovation in high-speed IO designs, setting new industry benchmarks. Facilitating cross-functional collaboration to achieve project milestones efficiently. Contributing to the successful launch of differentiated products in the market. Ensuring that our products meet the highest quality standards and customer expectations. What You'll Need: BTech/MTech in Electrical Engineering or a related field. 8-15 years of experience in analog design and high-speed IO designs in advanced technologies. Proficiency in analog design fundamentals and device physics. Expertise in high-speed IO designs for memory interface PHY IPs (DDR/HBM/UCIe). Knowledge of JEDEC requirements for memory interfaces and standards. Understanding of ESD and reliability concepts. Familiarity with signal integrity and power integrity. Excellent written, verbal communication, and interpersonal skills. Who You Are: A proactive and innovative problem solver. A collaborative team player with exceptional communication skills. Detail-oriented and committed to delivering high-quality results. Able to work independently and manage multiple projects simultaneously. Adaptable to fast-paced and dynamic work environments. The Team You'll Be A Part Of: You will be part of a highly skilled and collaborative team of engineers focused on developing cutting-edge memory interface PHY IPs. Our team is dedicated to pushing the boundaries of technology and delivering innovative solutions that meet the evolving needs of our customers. We work closely with cross-functional teams across the globe, ensuring that our products are of the highest quality and performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10118 Remote Eligible No Date Posted 18/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking a highly skilled Senior DevOps Engineer who is proactive and knowledgeable with a passion for cutting-edge technologies for the central software engineering organization at Synopsys. As an ideal candidate, you are experienced in driving engineering efforts related to Continuous Integration and Delivery (CI/CD), automated testing, and deployment across all phases of the Software Development Life Cycle. You are adept at implementing frameworks and best practices for deploying automation via pipelines into various environments including on-premises, cloud (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Your expertise lies in building platforms and frameworks that enable consistent, verifiable, and automated management of applications and infrastructure. You thrive in an Agile framework, identifying, creating, designing, and integrating processes for repeatable, automated software delivery. You are an advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. Your strong communication skills enable you to effectively design cross-functional deployments and triage efforts, and you possess excellent analytical and problem-solving abilities. Additionally, you are skilled in mentoring and providing oversight to other DevOps team members, guiding them in implementing recommended solutions for process automation and best practices. What You'll Be Doing: Driving engineering efforts related to Continuous Integration and Delivery (CI/CD) and automated testing and deployment across all phases of the Software Development Life Cycle. Implementing frameworks and best practices for deploying automation via pipelines into on-premises, cloud environments (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Building platforms and frameworks to create consistent, verifiable, and automatic management of applications and infrastructure in both on-premises and cloud infrastructure. Defining the development pipeline to ensure that software development flows match operational testing and deployment goals. Working within the Agile framework to identify, create, design, and integrate processes for repeatable, automated software delivery. Identifying and initiating the development of metrics and dashboards to monitor the adoption and maturity of DevOps practices. Advocating for innovation and automation, continuously seeking ways to improve CI/CD processes. Reviewing technical operations and providing mentoring and oversight to other DevOps team members in implementing recommended solutions for process automation and best practices. The Impact You Will Have: Enhancing the efficiency and effectiveness of our CI/CD pipelines to ensure high-quality software delivery. Enabling consistent and automated management of applications and infrastructure, improving reliability and scalability. Streamlining the software development lifecycle, ensuring alignment with operational testing and deployment goals. Driving the adoption and maturity of DevOps practices through the development of metrics and dashboards. Fostering a culture of innovation and automation within the engineering team. Mentoring and guiding other DevOps team members, enhancing their skills and knowledge. What You'll Need: Bachelor's or Master's degree in Engineering streams such as Computer Science, EEE, ECE, IT, or equivalent. At least 5 years of overall software development/deployment/infra experience. Cloud and other architect-level industry certifications (AWS, GCP, Azure, Security, etc.). 3-5 years of DevOps experience in modern tech stack to support products in the cloud. 2+ years of scripting/automation experience with Bash, Python, Perl, and/or other scripting languages. Strong CI/CD experience with code build, source control, testing, continuous integration, and delivery using standard DevOps CI/CD tools (Jenkins, Git). 3+ years of experience with containerization, source control (Docker/Docker Hub/Helm), and container orchestration (Kubernetes, Docker Swarm). Familiarity with programming languages (C/C++/Java). Familiarity with build tools (Make, CMake, Maven, Gradle) and dependency management (Conan). Experience developing Ansible Playbooks/Jenkins automation for infrastructure automation. Proficiency in multiple DevOps-related tools and technologies (JIRA, Confluence, GitHub/Azure, Jenkins, Ansible, Prometheus, Grafana, ELK). Who You Are: A proactive and knowledgeable engineer with a passion for cutting-edge technologies. An advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. A strong communicator, able to effectively design cross-functional deployments and triage efforts. An excellent problem solver with strong analytical skills. A mentor and guide, capable of providing oversight and guidance to other DevOps team members. The Team You'll Be A Part Of: You will be part of a dynamic and innovative central software engineering organization at Synopsys. The team is focused on driving engineering efforts and automating processes to deliver high-quality EDA products. We work collaboratively within an Agile framework, continuously seeking ways to improve and innovate in the field of DevOps.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Business Analyst with over 10 years of experience in IT, including at least 7 years in software testing and quality-related roles. Your expertise in Tricentis Tosca automation, particularly with SAP, Salesforce, Oracle CPQ, APIs, and web applications, sets you apart. You have a deep technical knowledge and understanding of software testing best practices and are proficient in automating User Experience (UX) for web-based, API, and desktop applications, including Vision AI+. You excel in test data management, continuous integration/continuous deployment (CI/CD) pipelines, and integrating Tricentis Tosca with QTest. Your leadership experience in test automation, collaborative mindset, and excellent communication skills make you an invaluable asset to any team. You are customer-centric, always seeking to deliver unique solutions, and you thrive in agile environments. You are open to learning new skills and technologies to stay ahead in a dynamic industry. What You'll Be Doing: Designing and developing Test Automation Frameworks, approach, and methodologies for large enterprise projects. Creating, maintaining, and executing end-to-end test cases, test scripts, and test data. Defining test automation strategy, best practices, project structure, and review processes. Performing test infrastructure setup, upgrades, and migrations, including Tricentis Tosca. Managing users, projects, and test portfolios using Tosca Server and Tosca Commander. Integrating Tricentis Tosca with third-party tools. Conducting regular reviews and maintenance of the test portfolio to ensure adherence to best practices. Defining upgrade and maintenance approaches and performing necessary upgrades and migrations. Collaborating effectively with global cross-functional teams and stakeholders. Mentoring and guiding team members on test automation best practices. The Impact You Will Have: Enhancing the quality and reliability of software products through robust automation frameworks. Streamlining testing processes, leading to faster time-to-market for our solutions. Ensuring seamless integration of Tricentis Tosca with other tools and platforms. Driving continuous improvement in testing methodologies and practices. Providing leadership and mentorship to junior team members, fostering a culture of excellence. Contributing to the overall success and innovation of Synopsys technology offerings. What You'll Need: Minimum 7 years of experience in Tricentis Tosca automation with SAP, Salesforce, Oracle CPQ, APIs, Web applications, etc. Expertise in automating User Experience (UX) for Web-based, API, and Desktop applications, including Vision AI+. Proficient in Test Data management using Tricentis Data Services (TDS) and Tricentis Test Case Design (TCD). Experience in DEX Configuration & Execution. Ability to set up Continuous Integration/Continuous Deployment (CI/CD) pipelines with Tricentis Tosca. Expertise in QTest integration with Tosca Certifications TRICENTIS Certified SAP Testing Specialist TRICENTIS Certified Tosca Architect TRICENTIS Certified Automation Engineer TRICENTIS Certified QTest Specialist TRICENTIS Certified Test Design Specialist Who You Are: As a professional with a sophisticated understanding of software testing and automation, you possess excellent written and verbal communication skills, enabling you to effectively engage with diverse audiences. You have a customer-centric approach, always striving to deliver unique and impactful solutions. Your collaborative mindset allows you to work seamlessly within global cross-functional teams, and your openness to learning new skills and technologies ensures you remain at the forefront of industry advancements. You are a proactive leader, advocating for test-driven development (TDD) practices and driving necessary changes to achieve optimal results. The Team You'll Be A Part Of: You will join a dynamic team of forward-thinking professionals dedicated to advancing software testing and automation practices. The team focuses on integrating cutting-edge technologies and methodologies to enhance the quality and reliability of our software products. Collaboration, innovation, and continuous improvement are at the core of our team's values, and we strive to create an environment where every member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job description (VC Spyglass Lint Technology on VC Platform) Responsible for designing, developing, troubleshooting the core VC-Static engine, which is integral part of Lint Design and develop Lint standard and customized Lint checks using VC Platform technologies for analysis, synthesis and simulations. Will be working closely with other teams both locally and globally Design and development of state of the art EDA tools involving development in one or more of the following areas-: developing new and innovative algorithms in the area of electronic design automation. Skills Required 4 to 10 years of Software development experience Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Fluent in C++ with work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Ability to develop new architecture Knowledge on GenAI is Value added Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success Quality focus one who believes in quality and wants to make a difference Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10151 Remote Eligible No Date Posted 21/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated professional with a strong technical background in analog and mixed-signal (A&MS) layout design. You thrive in collaborative environments, working closely with cross-functional teams to deliver high-quality layout designs. Your expertise in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler, allows you to create and optimize complex layouts efficiently. You are well-versed in physical verification processes and design rule checks, ensuring the integrity and manufacturability of your designs. Your problem-solving skills and systematic approach enable you to tackle challenges effectively. You are a lifelong learner, staying updated with the latest industry trends and advancements in A&MS layout design. Your excellent communication and interpersonal skills make you a valuable team player, contributing to the success of your projects and the organization as a whole. What You'll Be Doing: * Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-standard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturability. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems. * Enhance the manufacturability and reliability of our silicon lifecycle monitoring solutions. * Drive innovation in layout design methodologies and best practices. * Collaborate effectively with circuit designers to meet design specifications and constraints. * Contribute to the overall success of the rapidly expanding PVT IP group. * Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors. What You'll Need: * Bachelor's or master's degree in electrical engineering or a related field. * 5+ years of experience in A&MS layout design for integrated circuits. * Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. * Exceptional knowledge of layout design methods, techniques, and methodologies. * Experience with physical verification tools, such as Calibre or Assura. * Understanding of semiconductor process technologies and their impact on layout design. * Excellent problem-solving and systematic skills. * Ability to work effectively in a team-oriented environment. * Good communication and interpersonal skills. Who You Are: You are a dedicated and detail-oriented professional with a passion for A&MS layout design. Your ability to work collaboratively with cross-functional teams and your strong technical skills make you an asset to any project. You are proactive in staying updated with the latest industry trends and continuously seek to improve your knowledge and skills. Your excellent communication and interpersonal skills enable you to contribute effectively to team discussions and design reviews. The Team You'll Be A Part Of: You will be part of the rapidly expanding PVT IP group at Synopsys, a team dedicated to developing cutting-edge PVT Sensor IPs for SOC subsystems. This team is at the forefront of innovation, working on custom layout designs for Process, Voltage, Temperature, Current, and Droop sensors. You will collaborate with talented professionals who share your passion for excellence and innovation in layout design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned VLSI professional with extensive experience in product engineering management. Your background includes at least eight years of hands-on experience in VLSI product engineering, with a deep understanding of analog and digital SOC design flows. You have a proven track record of working on various technology nodes and driving product innovation. Your expertise spans across RTL Development, RTL Verification, and RTL to GDS flow, making you a versatile asset to any team. You excel in customer-centric roles, adept at managing multiple projects and setting priorities effectively. Your communication skills, both written and verbal, are top-notch, and you have a knack for interfacing with different levels of an organization. You are well-versed in database management and maintaining data cleanliness across product portfolios. If you are looking for a new challenge and are passionate about driving product success in the VLSI domain, we would love to connect with you. What You'll Be Doing: Collaborating with cross-functional teams to drive product success. Developing and executing product engineering strategies. Serving as the technical interface between teams. Interacting with Sales and Pre-Sales teams. Buildingtimeplansand schedules for product development. Ensuring customer satisfaction by addressing and prioritizing issues effectively. The Impact You Will Have: Driving the success of our VLSI products through strategic engineering management. Enhancing product innovation by working on various technology nodes. Improving customer satisfaction through effective communication and issue resolution. Ensuring seamless technical interfacing between cross-functional teams. Contributing to the development of high-performance silicon chips and software content. Supporting the sales process by providing technical insights and solutions. What You'll Need: Minimum 5 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes. Ability to manage multiple projects and set priorities effectively. Who You Are: Customer-centric with excellent communication skills. Able to interface with different levels of an organization. Proficient in database management and maintaining data cleanliness. Experienced in buildingtimeplansand schedules. Knowledgeable about industry trends and emerging technologies in VLSI. The Team You'll BeAPart Of: You will be part of a dynamic and innovative project management team dedicated to driving product success in the VLSI domain. Our team collaborates closely with cross-functional teams, including Sales, Pre-Sales, and technical experts, to ensure the successful development and delivery of high-performance silicon chips and software content. We are passionate about continuous technological innovation and strive to create a collaborative and supportive work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10335 Remote Eligible No Date Posted 26/03/2025 Alternate Job Titles: - Senior Digital Verification Engineer - Sr Staff ASIC Verification Engineer - Senior RTL Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You'll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You'll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role. The Team You'll Be A Part Of: You will join the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP cores used in various end-customer applications. You will work closely with architects, designers, and verification engineers across multiple international sites, fostering a collaborative and innovative environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and experienced Program Manager with a proven track record in the semiconductor industry. With 7-10 years of experience, you bring a wealth of knowledge in SoC design flow, IC manufacturing, process technology, and the signoff process. Your ability to communicate effectively at all levels of the organization, coupled with your exceptional interpersonal and teamwork skills, sets you apart. You thrive in a fast-paced environment, adept at prioritizing and managing multiple projects simultaneously while meeting deadlines. Your background in program management in IPs and experience with tools like JIRA make you an ideal candidate. You have a customer-centric approach, with prior experience in customer interfacing or support, and a knack for developing and maintaining key performance indicators to measure program effectiveness. What You'll Be Doing: Acting as the focal point of contact and managing internal communications relating to the program, including customer interactions. Coordinating with cross-functional teams spanning geographical and organizational boundaries to manage requirements and changes in the program. Driving day-to-day execution of key programs: directing schedules, identifying and escalating issues, driving problems to resolution, and managing risk. Effectively prioritizing and tracking multiple projects simultaneously using tools like JIRA. Collaborating with stakeholders to define project scope, objectives, and deliverables. Leading program and change management initiatives for audits and developing key performance indicators (KPIs) to measure effectiveness. The Impact You Will Have: Ensuring seamless internal and external communication for program success. Facilitating cross-functional collaboration to meet project goals and timelines. Driving the resolution of issues and managing risks to maintain project momentum. Enhancing program efficiency through effective prioritization and management of multiple projects. Contributing to the development of clear and comprehensive project requirements and specifications. Improving audit program effectiveness through the creation and maintenance of KPIs. What You'll Need: BE or equivalent with 7-10 years of experience in the semiconductor industry. Background in program management in IPs. Knowledge of SoC design flow, IC manufacturing, process technology, and signoff process. Experience communicating at different levels of the organization. Proficiency in using tools like JIRA. Who You Are: You are a proactive and organized individual with a strong ability to lead and align cross-functional teams. Your exceptional verbal and written communication skills enable you to effectively convey complex information. You are detail-oriented and excel in a collaborative environment, consistently delivering high-quality results. Your customer-centric approach and ability to manage multiple projects simultaneously make you a valuable asset to our team. The Team You'll Be A Part Of: You will join a dedicated team focused on driving program management excellence within the semiconductor industry. Our team collaborates closely with various departments and stakeholders to ensure the successful execution of projects and programs. We are committed to fostering a supportive and innovative work environment where every team member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10560 Remote Eligible No Date Posted 08/04/2025 Analog Design, Sr Engineer-10560 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols Analog Circuit Design - CMOS circuit design and layout methodology & flow. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. What You'll Be Doing: DDR/HBM Memory Interface I/O Circuit and layout design including GPIO and Special IO's. - Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications. What You'll Need: * Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design. * Experience Required: 1 - 3 yrs Who You Are: * Creative and results-oriented, capable of managing multiple tasks concurrently. * Strong verbal and written communication skills in English. * Ability to work collaboratively across teams to deliver solutions to customers. * Strong analytical, reasoning, and problem-solving skills. * Willingness to travel occasionally to support customer engagements. The Team You'll Be A Part Of: The team focuses on enabling our Interface IP customers to integrate the IP into their SoC and assist them through their design flows, debugging critical issues, and supporting silicon bring-up. This collaborative team works closely with customers to ensure the successful deployment of Synopsys leading Interface IP products in various market segments. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.