291 Chip Design Jobs - Page 3

You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success You are committed to upholding Synopsys culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond What you'll Be Doing: Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs. Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle. Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability. Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths. Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows. Contribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time. The Impact You Will Have: Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market. Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization. Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth. Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions. What you'll Need: Extensive hands-on experience with DFT methodologies, including scan insertion and ATPG for complex ASIC designs. Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites. Strong understanding of digital logic design, RTL coding, and verification principles. Demonstrated ability to debug and resolve DFT-related issues across multiple project phases. Solid scripting skills (eg, TCL, Perl, Python) to automate design and test flows. Who You Are: Collaborative team player who communicates effectively across functions and cultures. Proactive problem solver, comfortable with ambiguity and rapid change. Detail-oriented and highly organized, with a commitment to delivering high-quality results. Inclusive and open-minded, eager to share knowledge and mentor others. Self-motivated and driven by curiosity, with a continuous learning mindset.

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 6 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future. What you'll Be Doing: Design and development of transistor-level analog and mixed-signal layout. Device level floorplan, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. Create and review layout documents to ensure they meet quality standards and are delivered on time. Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Collaborate with cross-functional teams to ensure successful project execution. The Impact You Will Have: You will drive the design and development of high-quality analog and mixed-signal layouts. Your expertise will ensure the successful implementation of CMOS and FINFET technologies. Through effective troubleshooting, you will contribute to achieving clean physical verification results. Your attention to detail will ensure that layout documents meet quality standards and deadlines. By managing project schedules and milestones, you will help deliver projects on time. Your collaboration with cross-functional teams will enhance project success and innovation. What you'll Need: Bachelors or Masters degree in Electrical Engineering or a related field. Minimum 6 years of experience in Analog and Mixed Signal Circuit Layout. Proficiency in Analog Layout Flow from device placement to GDS release. Strong knowledge of CMOS and FINFET technologies and semiconductor device physics. Experience with EDA tools for custom mixed-signal layout flows. Understanding of CMOS fabrication technology and deep sub-micron effects on layout. Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout. Passion for learning and exploring new techniques. Who You Are: Detail-oriented and self-directed with excellent problem-solving skills. Strong communication skills for effective collaboration with cross-functional teams. Ability to manage multiple projects and meet deadlines effectively. Innovative thinker with a passion for technological advancement. Team player who thrives in a dynamic and fast-paced environment.

Emulation Verification Engineer in Pune, MH, India Description By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: As a part of the Emulation Team at Ampere, you will be part of verification of the next generation of microprocessor cores on hardware emulation platform by developing and deploying new capabilities and test content to accelerate bug finding in pre-silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Design Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements. The Emulation Team at Ampere Computing comprises of stellar folks who have dedicated themselves to the art and fun of design verification. We are a tight knit, fast-paced team who work extremely closely with our design and architecture partners to ensure no bug is left behind. What youll achieve: Your responsibilities may include, but are not limited to, the following: Be part of the emulation verification execution team and be responsible for planning, development, and execution of test content in varied domains including system stress. Work in collaboration with design and architecture teams to root-cause failures using advanced debugging techniques. Develop high quality emulation test plans comprising of BareMetal content and OS based content for flushing even the most corner-case bugs. Create emulation models from RTL to run test content, using industry standard emulation platform technology. Review architecture and microarchitecture specs and influence design/microarchitecture decisions Partner with emulation vendor to debug and quickly resolve blocking issues in the emulation technology as required Verify performance and functionality of GPU/AI hardware , drivers, features ,application and tools. About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Knowledge about AI processor/GPU architecture , Linux systems development and memory consistency models in AArch64 and/or x86 and concurrency. Knowledge about GPU Stress and functional test development. Experience in GPU compute programming or parallel programming. Demonstrated ability to rapidly learn new technologies and apply them effectively. Experience developing bare-metal content using C/C++ and assembly language for verification. ARM assembly expertise preferred. Experience with Linux kernel development, device drivers and user space programming, FW development and debugging Experience in one of the protocols in preferred - Ethernet/USB/SATA/LPDDR/HBM. Experience debugging failures using innovative debug practices and familiarity with tools such as Verdi to debug RTL issues. Working experience with emulation technology of Zebu, Palladium or Mentor Veloce is strongly recommended. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Emulation Verification Engineer in Bangalore, KA, India Description By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: As a part of the Emulation Team at Ampere, you will be part of verification of the next generation of microprocessor cores on hardware emulation platform by developing and deploying new capabilities and test content to accelerate bug finding in pre-silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Design Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements. The Emulation Team at Ampere Computing comprises of stellar folks who have dedicated themselves to the art and fun of design verification. We are a tight knit, fast-paced team who work extremely closely with our design and architecture partners to ensure no bug is left behind. What youll achieve: Your responsibilities may include, but are not limited to, the following: Be part of the emulation verification execution team and be responsible for planning, development, and execution of test content in varied domains including system stress. Work in collaboration with design and architecture teams to root-cause failures using advanced debugging techniques. Develop high quality emulation test plans comprising of BareMetal content and OS based content for flushing even the most corner-case bugs. Create emulation models from RTL to run test content, using industry standard emulation platform technology. Review architecture and microarchitecture specs and influence design/microarchitecture decisions Partner with emulation vendor to debug and quickly resolve blocking issues in the emulation technology as required Verify performance and functionality of GPU/AI hardware , drivers, features ,application and tools. About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Knowledge about AI processor/GPU architecture , Linux systems development and memory consistency models in AArch64 and/or x86 and concurrency. Knowledge about GPU Stress and functional test development. Experience in GPU compute programming or parallel programming. Demonstrated ability to rapidly learn new technologies and apply them effectively. Experience developing bare-metal content using C/C++ and assembly language for verification. ARM assembly expertise preferred. Experience with Linux kernel development, device drivers and user space programming, FW development and debugging Experience in one of the protocols in preferred - Ethernet/USB/SATA/LPDDR/HBM. Experience debugging failures using innovative debug practices and familiarity with tools such as Verdi to debug RTL issues. Working experience with emulation technology of Zebu, Palladium or Mentor Veloce is strongly recommended. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

You will be part of a big MNC as a Semiconductor Domain Consultant, responsible for utilizing your expertise in semiconductor manufacturing processes, chip design, and testing methodologies. Your role will require a strong understanding of semiconductor technologies such as CMOS, memory devices, RF, power semiconductors, and sensors. Additionally, you will need experience with semiconductor supply chain management, market analysis, and knowledge of industry standards, regulations, and certifications. Your responsibilities will include effective communication, presentation, and client relationship management. You should be able to work both independently and collaboratively as part of a team. Project management experience would be beneficial for this role. It would be advantageous to have experience with advanced semiconductor packaging technologies, familiarity with semiconductor EDA tools and software, knowledge of semiconductor equipment and infrastructure, and experience in emerging fields like AI/ML hardware accelerators, quantum computing, and IoT. Join us at this exciting opportunity located PAN India and contribute your skills to the dynamic world of semiconductor technology.,

As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 12+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. You thrive in a collaborative environment and are excited to work closely with global teams on the latest technology nodes. You have a strong understanding of semiconductor device physics and digital design, and you possess a solid foundation in CMOS fundamentals. Your familiarity with Unix/Shell/Python/TCL is an added advantage, and you are eager to leverage these skills to contribute to innovative projects. Your attention to detail and problem-solving abilities make you an ideal candidate for this role. What You ll Be Doing: Designing and developing physical IP such as SERDES, DDR, and/or Memory as part of the Logic Libraries team. Collaborating with global teams to implement and optimize layout designs on the latest technology nodes. Utilizing your understanding of CMOS fundamentals to ensure high-quality and efficient design processes. Employing Unix/Shell/Python/TCL scripting to automate and enhance design workflows. Conducting design reviews and providing feedback to improve overall design quality and performance. Staying updated with the latest industry trends and technological advancements to ensure cutting-edge designs. The Impact You Will Have: Contributing to the development of high-performance silicon chips that power a wide range of applications. Enhancing the efficiency and reliability of physical IP design processes. Supporting the advancement of semiconductor technology through innovative layout designs. Collaborating with global teams to achieve project milestones and deliver high-quality designs. Improving the overall performance and functionality of Synopsys technology solutions. Driving the continuous technological innovation that shapes the future of the industry. What You ll Need: Strong understanding of semiconductor device physics and digital design principles. Solid foundation in CMOS fundamentals. Experience with Unix/Shell scripting and familiarity with Python/TCL. Proficiency in layout design and development of physical IP. Ability to work collaboratively with global teams and communicate effectively. Who You Are: Detail-oriented with strong analytical and problem-solving skills. Innovative and eager to stay updated with industry trends and advancements. Collaborative team player with excellent communication skills. Proactive and able to manage multiple tasks effectively. Passionate about semiconductor technology and its applications

Individual Contributor role for Technical leader with 10+ years of experience in Analog and Power IC development within 2. 6B$ Power Business Unit at Renesas. Primary responsibilities include leading the design and development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas s massive Power product portfolio. In the Technical leader role, candidate will be directly responsible for end-to-end IC design (from specifications to PRA). Will be expected to work with other team members to do successful Chips along with mentoring the junior members. This is an IC role with complete focus on product development and no people management. Essential Functions: Must have led and should be experienced of developing multiple Power ICs with Switching Converters, starting from system level specifications and taking ICs to production. Identify and resolve technical challenges and risks. Provide technical expertise and mentorship to junior engineers. Able to lead group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs. Must be proficient in designing complete switching converters and all involved I/Ps. Should be fully aware of all challenges pertaining to high current/power switching converters design including Noise, Power dissipation etc and their mitigation. Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability. Should be able to lead and guide development, integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must. Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. Should be able to architect the IC and break down System/Chip-top level requirements into block level specifications and then work with Team members and develop the blocks, integrate the blocks into Top level and ensure desired performance. Must have good understanding of commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each. Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance. Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance. Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges. Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy. Should have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC Minimum Requirements: Bachelor s or master s degree in electrical engineering 10+ years in Analog Circuit Design. Solid understanding and design experience of complex analog designs with full ownership. Chip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production. Must be a technical leader & natural team player, mentor and should strive towards fostering a highly creative and productive working environment

Energetic, experienced, and organized, you are a writer who thrives in a vibrant environment and is passionate about cutting-edge technology You have a knack for turning complex technical information into clear, concise, and user-friendly documentation With a strong background in technical writing within the software or hardware industry, you bring a blend of creativity and precision to your work You are a team player who can also work independently, and you take pride in delivering high-quality content on time Your excellent communication and interpersonal skills enable you to collaborate effectively with engineers and other stakeholders You are always eager to learn and adapt to new technologies, ensuring that your documentation remains relevant and up-to-date If you care about doing a good job, about details, and about contributing to a dynamic team, Synopsys is the place for you What You ll Be Doing: Planning, organizing, writing, and editing a variety of customer documentation. Collaborating with engineers to understand product functionalitie s and features. Creating user manuals, reference guides, and online help content in various formats. Ensuring documentation is accurate, clear, and comprehensive. Maintaining and updating existing documentation to reflect product updates. Utilizing authoring tools such as FrameMaker and Oxygen to produce high-quality content. The Impact You Will Have: Empower customers to effectively use and optimize Synopsys products. Enhance user experience through clear and accessible documentation. Support product adoption and customer satisfaction. Contribute to the success of product releases with timely and accurate documentation. Facilitate better communication and understanding between customers and the engineering team. Help maintain Synopsys reputation as a leader in semiconductor IP solutions. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering disciplines. Other technical disciplines considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solvin g skills with strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Excellent English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player with the ability to work independently. Detail-oriente d and committed to delivering high-quality work. Proactive and able to take ownership of projects with minimal supervision. The Team You ll Be A Part Of: You will be part of a dynamic and experienced Technical Publications team that works closely with world-class engineers to create essential customer documentation. Our team is committed to empowering customers worldwide with comprehensive and user-friendly content that enhances their experience with Synopsys products.

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You Are: You are an accomplished analog design engineer with a passion for advancing technology and enabling world-class silicon solutions. With over5 years of hands-on experience in custom analog design, you have mastered the nuances of analog circuit building blocks, including amplifiers, reference circuits, and clock generators. You thrive in collaborative environments, working seamlessly with design and CAD teams to refine simulation methodologies that elevate design verification efficiency. Your technical toolkit is robust, featuring expertise in industry-standard verification and simulation tools such as HSPICE, Primesim, and VCS, as we'll as proficiency in scripting and automation using Perl, Python, and TCL. Your approach is both analytical and creative you'relish the challenge of optimizing analog circuits for performance, reliability, and scalability. You are also an effective communicator, eager to share your knowledge through peer support and training, thereby fostering a culture of innovation and continuous learning. Your adaptability ensures you stay at the forefront of evolving industry trends and methodologies, and your proactive mindset drives you to seek out opportunities for process improvement. Above all, you believe in the power of teamwork and mentorship, empowering those around you to achieve collective success. What you'll Be Doing: Designing, developing, modifying, and evaluating physical IP such as SERDES, DDR, and Memory. Collaborating with design and CAD teams to develop and deploy advanced simulation methodologies. Automating design and simulation flows/tasks using scripting languages and existing tools. Providing technical support and training to team members to enhance overall capabilities. Analyzing and optimizing analog circuit building blocks, including amplifiers, reference circuits, and clock generators, for performance and efficiency. Ensuring efficient use of verification tools to accelerate and improve the accuracy of design verification processes. The Impact You Will Have: Enhancing the efficiency and accuracy of analog design verification, leading to faster, more reliable silicon development. Contributing to the creation of cutting-edge high-performance silicon chips and software content that power next-generation technologies. Driving innovation in analog circuit design and simulation methodologies, setting industry benchmarks. Streamlining the design and development cycle, reducing time-to-market for critical IP blocks. Building team expertise through training and support, fostering a collaborative and high-performing culture. Playing a pivotal role in the continued success and technological leadership of Synopsys. What you'll Need: BE/MTech in Electronics or a related field. 5+ years of proven experience in Custom Analog Design. Proficiency with industry-standard design verification and simulation tools (HSPICE, Primesim, VCS). Strong scripting and automation skills using Perl, Python, and TCL. In-depth knowledge of analog circuit building blocks, including amplifiers, reference circuits, and clock generators. Who You Are: A collaborative team player who excels in cross-functional environments. An effective communicator with the ability to share complex technical concepts clearly. A problem-solver with keen attention to detail and a drive for innovation. A proactive learner who actively seeks out new technologies and methodologies. A mentor and coach who supports the growth and development of colleagues. An analytical thinker skilled at evaluating and addressing complex engineering challenges. The Team you'll Be A Part Of: You will join a dynamic and innovative team dedicated to analog design and verification. Our culture thrives on collaboration, creativity, and continuous improvement. We work closely with multiple departments to ensure seamless integration and optimal performance of our products, playing a significant role in Synopsys broader technology strategy and success.

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

Where Staff Applications Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 6051 Remote Eligible No Date Posted 20/03/2025 Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips faster. We re the world s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance eliminating months off their project schedules. Were looking for an Applications Engineer to join our team. Does this sound like a good role for you This is an exciting opportunity to be part of applications engineering team that supports the industry leading Static Timing Analysis tool, Primetime. The primary focus of the Application Engineer (AE) is to drive increased usage of the product in both pre-sale and post-sale capacity. Pre-sales tasks include competitive benchmarks and evaluation, articulating the superiority to our customer s design team and management. Post-sales tasks include customer training, tape-out support and advance collaboration initiatives for product enhancements. The job involves working closely with users/customers and multiple organizations like R&D, marketing, sales among others. Key Qualifications Synopsys STA tool, PrimeTime experience and knowledge are required Knowledge of timing corners/modes, process variations and signal integrity related issues are required Familiarity with synthesis, Physical design, extraction and ECO methodology is desired Strong TCL knowledge is preferred Excellent verbal and written communication skills are mandatory. Prior customer facing role is a plus BSEE or equivalent, required with 6-7 years of experience, or MSEE, or equivalent with 4-5 years of experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

cv shared to shilpa.srivastava@orcapod with Recruiter Semi conductor industry Role & responsibilities candidate should have experience in hiring for semi conductor industries screening of resumes sourcing of candidates

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 5 years of experience with physical design. Experience with Python or C++. Experience with machine learning. Preferred qualifications: 10 years of experience in synthesis and physical design. Experience in various machine learning algorithms from logistic regression to neural networks and reinforcement learning. Understanding of algorithms and data structures. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Machine Learning Engineer for the Google silicon organization, you will contribute to improving SoC Performance, Power, and Area (PPA) using machine learning techniques. You will apply your experience to solve technical issues and drive improvements in Power, Performance, Area, and Schedule. You will directly impact logic design and optimization, floorplanning, place and route, clock and power planning, timing analysis, Power Delivery Network (PDN) analysis, and more. You will collaborate across Alphabet, working with design, CAD, and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Google s AI solutions into chip design, collaborating with internal teams, Google DeepMind, and other teams within Google to explore and apply solutions that improve chip design PPA or reduce cycle time.

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 4 years of experience with physical design flow such as floor planning, place and route, or physical verification. Experience with low-power design techniques, such as power gating, clock gating, or voltage scaling. Preferred qualifications: Experience in using Machine Learning (ML) in physical design. Knowledge of machine learning algorithms from logistic regression to deep neural networks and reinforcement learning. Knowledge of data structures and algorithms. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will contribute to improving Power Performance Area (PPA) using machine learning techniques. You will use the experience of physical design and machine learning to solve technical problems and improve on Power, Performance, Area and Schedule. You will work on design and optimizations, floorplan, place and route, clock and power planning, timing analysis, and Power Delivery Network (PDN) analysis. You will collaborate across Alphabet working with design, CAD and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Artificial Intelligence (AI) solutions into chip design, work with internal teams, Google DeepMind and other teams to explore solutions and apply to improve chip design PPA or cycle time.

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 8 years of experience in high-performance design, multi-power domains with clocking. Experience in multiple SoCs with silicon success. Experience with Verilog or System Verilog language. Preferred qualifications: Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software. Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features. Interact closely with architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and performance, power, and area (PPA) for sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in ASIC Chip Design. 5 years of experience with hardware electronic design automation tools. Experience in Python/C++ programming. Experience in writing code and design practices. Preferred qualifications: Experience planning and deploying new tools and flows to users. Experience in AI/ML methods for ASIC development. Knowledge of chip design processes such as verification, design, and implementation. Ability to present and explain novel methods to users. Strong programming/software skills like C/C++/Python. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will help deliver products that have a substantive impact on the technical infrastructure. You will provide leadership in an innovative and fast-paced environment with a focus on infrastructure for chip design. You'll also lead complex technical projects from the concept/planning stage through execution and closure. You will enable the wider team to deliver designs of different application areas, including ML/AI acceleration by developing tools relying on AI/ML techniques. You will lead end-to-end chip design process improvement projects. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Partner with the Google Deepmind team to incorporate AI/ML techniques in chip design methodology and integrate into development flow. Partner with Chip Project teams to influence and standardize methodology across projects and functional areas (e.g., Design, Verification, Emulation, and other front end domain). Propose, design, and implement software automation addressing bottlenecks in today's ASIC and SoC EDA flow. Perform or guide technical evaluations of tools and their AI capabilities, and drive planning for possible deployment. Lead the development of internal software tools and automation efforts, participate in design reviews, and engage in influencing and scheduling trade-off discussions. Collaborate to identify and create strategic opportunities for improved chip design across Google. Work directly with a hardware team on projects-prototype and deploy tools to make a positive impact on Google's chip hardware development process.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design integration. Experience in Verilog or Systemverilog coding. Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features. Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Standard Cell Characterization- Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11933 Remote Eligible No Date Posted 06/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous R&D Engineering Senior Engineer with a profound understanding of semiconductor technologies. You thrive in dynamic environments where your expertise in MOSFET and FINFET technologies can shine. With a keen eye for detail and a dedication to quality, you excel at characterizing and modeling standard cells for various technologies and foundries. You are adept at conducting quality analysis of characterized liberty and Verilog models, ensuring timing, power, and functionality standards are met. Your experience with PrimeLib, Hspice, PrimeSim, and Finesim tools positions you as a key player in the validation process. You are committed to delivering on time and quality releases, providing daily status updates, and continuously improving processes. Your collaborative spirit and ability to communicate effectively make you a valuable team member, ready to contribute to groundbreaking innovations. What You ll Be Doing: Characterizing and modeling standard cells for various technologies and foundries. Conducting quality analysis of characterized liberty and Verilog models in terms of timing, power, and functionality. Validating characterization and simulation tool versions including PrimeLib, Hspice, PrimeSim, and Finesim. Providing daily status updates on project progress. Ensuring timely and quality releases of projects. Collaborating with cross-functional teams to enhance design and verification processes. The Impact You Will Have: Enhancing the accuracy and efficiency of standard cell models across various technologies. Improving the quality and reliability of characterized models in terms of timing, power, and functionality. Streamlining validation processes for characterization and simulation tools, ensuring robust tool versions. Contributing to the timely delivery of high-quality releases, meeting project deadlines and standards. Supporting technological innovation through meticulous analysis and validation. Fostering collaboration and knowledge sharing within cross-functional teams for continuous improvement. What You ll Need: 3+ Years of experience in Standard Cell Characterization Thorough knowledge of MOSFET and FINFET technologies. Experience with PrimeLib, Hspice, PrimeSim, and Finesim tools. Strong analytical skills for quality analysis of characterized models. Proficiency in characterizing and modeling standard cells for various technologies. Excellent communication skills for providing daily status updates and collaborating with teams. Who You Are: A detail-oriented professional with a strong analytical mindset. A proactive communicator, able to provide clear and concise updates. A collaborative team player, ready to work with cross-functional teams. A dedicated individual committed to delivering high-quality work on time. An innovative thinker, always looking for ways to improve processes and outcomes. The Team You ll Be a Part Of: You will be part of a dynamic and innovative team focused on advancing semiconductor technologies. Our team is dedicated to characterizing and modeling standard cells, ensuring the highest quality and reliability. We work collaboratively to validate and enhance our tools and processes, driving continuous improvement and technological innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Senior Software Engineer (C#, .NET Framework) Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 10126 Remote Eligible No Date Posted 09/04/2025 We Are: You Are: You are a highly passionate technical engineer with 2-3 years of object-oriented programming experience. You are driven by the desire to innovate and solve complex problems. You possess a strong foundation in programming with expertise in C#, .NET Framework, and WPF. Your understanding of data structures and algorithms allows you to develop robust and efficient solutions. You have a keen interest in power electronics and are excited about the opportunity to work on high-precision virtual prototyping tools. You are a team player, capable of working collaboratively with application engineers to enhance and maintain user experiences. Your attention to detail ensures that customer requirements are meticulously addressed, and you are adept at implementing regression test cases to ensure software reliability. What You ll Be Doing: Developing, implementing, and testing user experiences for high-precision virtual prototyping tools. Collaborating with application engineers to enhance existing user experiences and develop new ones. Designing and implementing solutions to address customer requirements and issues. Adding regression test cases to ensure software reliability and performance. Conducting what-if studies and generating best and worst-case results for power electronics simulations. Staying up-to-date with the latest advancements in power electronics and software development. The Impact You Will Have: Enhancing the user experience of Synopsys virtual prototyping tools, making them more intuitive and efficient. Accelerating the validation of software-defined vehicles through advanced simulation technologies. Contributing to the reduction of project schedules for customers, enhancing their productivity. Driving innovation in the field of power electronics through high-precision simulations. Ensuring the reliability and performance of Synopsys software solutions through rigorous testing. Supporting the development of cutting-edge technologies that shape the future of smart systems. What You ll Need: Bachelors degree in Computer Science or a related field. Strong programming skills in C#, .NET Framework, and WPF. In-depth knowledge of data structures and algorithms. Experience with object-oriented programming concepts. Interest or knowledge in power electronics. Who You Are: Collaborative team player with excellent communication skills. Detail-oriented with a strong problem-solving mindset. Adaptable and eager to learn new technologies and concepts. Proactive in addressing customer requirements and issues. Innovative thinker with a passion for technology and development. The Team You ll Be A Part Of: Our Technology and Product Development Group (TPG) is all about enabling our customers to adopt a software-first approach to building and testing high-performance embedded systems. We re the world s leading provider of solutions to accelerate software-defined vehicle (SDV) validation through Synopsys virtual prototyping and electronic digital twins technologies, eliminating months off customers project schedules. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Role & respon Responsibilities: Develop business accounts and customer projects, prepare strategies for sales, well position Product in front of customer. Reach out and do follow ups with customers from a variety of marketing campaigns to qualify potential business leads. Research targeted companies/contacts to position company products. Send personalized emails and make outbound calls to targeted accounts and contacts. Provide Project Managers with solid prospect background on opportunities to ensure high-quality prospect transition into the sales process. Execute the necessary daily activities to meet your weekly/monthly goals. Track all activity thoroughly in our CRM system to support account and management teams. Qualification: Developing business and building relationships over phone and email, with excellent interpersonal, verbal and written capabilities in English (professional proficiency) Flexible with working timing. Preferred candidate profile REQUIREMENT : Knowledge of VLSI is mandatory either frontend or backend. 4-5 years of relevant experience in the semiconductor industry (understand Chips and IPs, ASIC Design Flow etc.) Proven experience in Marketing and Sales within the semiconductor domain. Working knowledge of EVK's (Evaluation kit) Working knowledge of BLE, BT, wifi etc. Having experience of any of the chipset like - ST micro . Excellent verbal communication and listening skills. sibilities

People Operations, Sr Associate Bengaluru, Karnataka, India Apply Now Save Category: People Hire Type: Employee Job ID 11943 Date posted 07/04/2025 Share this job Email LinkedIn X Facebook ; We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A dedicated and detail-oriented professional with a passion for optimizing HR operations and processes. You thrive in dynamic environments and excel in managing employee lifecycle transactions, from onboarding to offboarding. With a minimum of 3-5 years of experience in People (HR) operations, you are well-versed in HRIS administration, particularly with tools like SuccessFactors or similar employee central systems. Your exceptional organizational skills, resourceful problem-solving abilities, and strong communication skills make you a valuable partner to stakeholders. You hold a BA/BS degree and have experience with ServiceNow, Microsoft Office suite, and project management tools. You are proactive, reliable, and committed to enhancing HR practices to benefit the organization. What You will Be Doing: * Collaborate with global cross-functional stakeholders to deliver relevant and impactful HR operation solutions. * Accurately perform employee lifecycle transactions/processes, including onboarding, offboarding, transfers/job status changes, time keeping, time off and leave, and extended workforce management in India and APAC. * Recommend, design, and draft employee lifecycle processes and procedures to enhance and optimize existing HR practices. * Be a trusted resource for HR systems, data, and process knowledge to interpret and analyze processes for driving HR operation enhancements. * Create, execute, and support delivery of various projects to standardize and strengthen HR practices across the organization. * Support new module roll-out and optimization initiatives to improve HR operations. The Impact You Will Have: * Streamline HR operations to improve efficiency and accuracy in employee lifecycle management. * Enhance the employee experience by ensuring seamless onboarding, offboarding, and other HR processes. * Contribute to the continuous improvement of HR practices and systems, benefiting the entire organization. * Build strong relationships with stakeholders by providing reliable and effective HR solutions. * Support the successful roll-out of new HR modules and initiatives, driving organizational growth and innovation. * Ensure compliance with HR policies and procedures, maintaining high standards of operational excellence. What You will Need: * Minimum 3-5 years of experience in People (HR) operations, process improvement, and HRIS administration in India, Taiwan, China and Japan * BA/BS degree. * Experience managing requests, workflows, developing knowledgebase, and reporting metrics using ServiceNow. * Exceptional detail orientation, organizational skills, and the ability to prioritize and manage multiple deadlines. * Proficiency with Microsoft Office suite and project management tools. Who You Are: * Resourceful problem-solver with the ability to troubleshoot issues independently and drive impactful solutions. * Excellent written and spoken communication skills. * A proactive and reliable team player. * Strong stakeholder partnering and operational skills. * Committed to continuous improvement and operational excellence. The Team You will Be A Part Of: You will be part of a dedicated HR team focused on optimizing people operations and enhancing HR practices. Our team values collaboration, innovation, and a commitment to excellence. We work closely with cross-functional stakeholders to deliver impactful HR solutions and support the growth and success of the organization. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs People Operations, Sr Associate Bengaluru, India People Physical Design Application Engineer, Sr Staff Zapopan, Mexico Engineering Applications Engineering, Sr Staff Engineer Bengaluru, India Engineering

Be responsible for Project Management for integrated GaN products / System Projects. Manage the activities to develop the required silicon drivers or controllers dies and the GaN HEMTs and combine these in one package. Coordinate and lead projects from requirements gathering through chip design, characterization, and qualification, all the way to volume ramp-up. Lead cross-functional and multicultural project teams from various locations, creating the energy and passion to reach ambitious project targets Take full project management responsibility for all project targets and plans (milestones, resources, risks, budget, costs) Facilitate timely project decision-making, ensure consistent progress, and lead through challenges while serving as a role model for the team. H andle the project in a fast and market-driven environment with a clear focus on the business objectives, support customer interactions as needed Own the project results, deliverables and success. Contribute to continuous improvement of the development process to be leaner and thus faster. You are best equipped for this task if you have: Passion to shape GaN development and -projects to drive them to success in a highly competitive environment. 5 years of experience in leading end to end semiconductor development projects with relevant functional experience. Must have driven projects from product definition to qualification and volume production Should have reasonable understanding of business case development processes and semiconductor product development budget. Should have worked with or lead project teams that include functional leads for product definition, design, design verification, test and characterization, application and marketing, quality and reliability and manufacturing including wafer fabrication and packaging. Demonstrated Project Management skills (IPMA-C certification is a plus). Experience of leading cross-functional teams in a matrix organization. Willingness to travel internationally from time to time, mainly to our locations in Europe and Asia. A degree in Electrical Engineering, System Engineering, Power Electronics, or comparable. Excellent English language and presentation skills

"> Search Jobs Find Jobs For Where Search Jobs GPU/HPC R&D Principal Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 7770 Remote Eligible No Date Posted 01/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate GPU R&D Engineer with a strong background in optimizing and implementing GPU-accelerated algorithms. You have a deep understanding of CUDA or similar technologies, and you excel in performance improvements and integration with existing tools. Your expertise in algorithms and data structures, combined with your collaborative skills, make you a valuable asset to any team. You are always eager to stay current on GPU technology trends and incorporate the latest advancements into your work. With at least 8 years of experience, you are ready to take on challenging projects and deliver optimal solutions rapidly, contributing to the fast-paced environment at Synopsys. What You ll Be Doing: Optimize existing GPU implementations for ILT software. Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT. Collaborate with cross-functional teams to ensure seamless integration of GPU features. Lead benchmarking and performance testing initiatives. Stay current on GPU technology trends and design the latest advancements into the system. Work closely with customers and hardware vendors to deliver optimal solutions swiftly. The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations. Drive innovation in GPU-accelerated algorithms for complex geometric data handling. Ensure the seamless integration of GPU features within existing Mask Synthesis tools. Lead initiatives that set new benchmarks for performance and reliability. Keep Synopsys at the forefront of GPU technology advancements. Accelerate the manufacturing of new chips by delivering rapid and optimal solutions. What You ll Need: Bachelors, Masters, or Ph.D. in Computer Science or a related field. At least 8 years of experience in GPU optimization and implementation. Advanced knowledge of CUDA or similar technologies. Proficiency in C/C++, Python, and distributed computing environments. Strong understanding of algorithms and data structures. Who You Are: Exceptional troubleshooting and collaborative skills. Passionate about staying up-to-date with the latest GPU technology trends. Detail-oriented and committed to delivering high-quality solutions. Strong communicator with the ability to work effectively in cross-functional teams. Innovative thinker who thrives in a fast-paced, dynamic environment. The Team You ll Be A Part Of: You will be part of a dedicated team of engineers focused on developing and optimizing ILT software. The team collaborates closely with customers, hardware vendors, and cross-functional groups within Synopsys to ensure the delivery of cutting-edge solutions. Together, we strive to push the boundaries of what is possible in the EDA industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!