You are a highly skilled and motivated Gen AI Platform Engineer with a passion for leveraging modern architectures, tools, and technologies. You excel in designing and developing scalable, modular solutions that enhance the efficiency and effectiveness of R&D efforts. Your deep understanding of distributed computing, cloud services, and container technologies allows you to create robust and secure platforms. You are collaborative, with excellent problem-solving and organizational skills. Your ability to incorporate AI and machine learning into your work sets you apart, and you are always looking to stay ahead of industry trends. Your effective communication skills enable you to work effectively with cross-functional teams and stakeholders, ensuring that user feedback is incorporated into the development process. What You will Be Doing: Designing and developing scalable, modular platform solutions that promote reuse and are easily integrated into our diverse product suite. Collaborating with cross-functional teams to understand their needs and incorporate user feedback into the platforms development. Establishing and Implementation of best practices for modern software architecture, including microservices, serverless computing, and API-first strategies and CI/ CD. Driving the strategy for containerization and orchestration using Docker, Kubernetes, or equivalent technologies. B enchmarking LLM models with varying loa d profile s to evaluate model performance. Developing Cloud native solutions for GenAI apps including Helm development, CRD, working with Kubernetes APIs, Storage class , PVCs, Services , Ingress controllers etc Handson Kubernetes monitoring Architecture including building Grafana dashboards, custom metrics, autoscaling etc. Hands on GPU Administration on Kubernetes including monitoring, multi-instance GPU etc. Incorporating AI and machine learning capabilities into the platform to facilitate smarter workflows and predictive analytics. The Impact You Will Have: Enhancing the efficiency and effectiveness of our R&D product development processes. Keeping our products at the forefront of the industry through the adoption of advanced technologies. Promoting reuse and integration across our diverse product suites . Promoting Automation of various applications build processes. Play a key role in cloud native transformation journey of legacy application stacks. Facilitating smarter workflows and predictive analytics through AI and machine learning. Ensuring the robustness, security, and compliance of our platform infrastructure. Driving innovation and continuous improvement within the platform engineering team. What You will Need: Bachelors or M asters degree in computer science , Engineering, or a related field. A minimum of 5 years of experience in software development. Strong development experience in Go (highly preferred) Python. Model management, etc ,. Deep understanding of distributed computing, CAP theorem, and system design tradeoffs. Proven expertise in cloud computing services (AWS, Azure, GCP), container technologies (Docker, Kubernetes). Linux Foundation certifications: CKA, CKAD , CKS (highly preferred). Experience with Generative AI, along with a working knowledge of various aspects such as GPUs, models, inference serving, and LLM Gateways, is highly desirable. Familiarity with AI/machine learning frameworks and tools, coupled with a keen interest in staying updated with emerging innovations, is also greatly valued. Background in working with CI/CD pipelines and familiarity with modern software delivery ecosystem (GitHub Actions, Azure DevOps, Harness.io, GitLab CI, etc.). Excellent problem-solving, organizational, and leadership skills. Effective communication abilities to effectively collaborate with internal teams and stakeholders. Who You Are: A proactive and self-motivated individual. A creative thinker with strong problem-solving skills. Highly organized and detail oriented. A team player with excellent interpersonal skills. Adaptable and able to thrive in a fast-paced environment.

"> Search Jobs Find Jobs For Where Search Jobs Senior Staff Product Validation Engineer - PD Formality Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10887 Remote Eligible No Date Posted 24/04/2025 We Are: You Are: You are a passionate and highly skilled engineer with a deep understanding of digital implementation and logic equivalence checking and a strong desire to lead product validation efforts. Your exceptional debugging skills and proficiency in software and scripting languages such as Perl, Tcl, and Python set you apart. With a keen eye for detail, you maintain high standards of product quality and excel in communication and leadership roles. You thrive in collaborative environments, working closely with cross-functional teams to develop and execute comprehensive validation plans. Your analytical mindset allows you to perform in-depth root cause analysis and proactively address potential issues, ensuring the readiness of products for customer deployment. You are an experienced professional with a B.Tech or M.Tech degree and a minimum of 6-8 years of related experience, ready to make a significant impact on our Formality tool. What You ll Be Doing: Execute and lead product validation of Synopsyss Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsyss Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You ll Need: B.Tech or equivalent and a minimum of 8 years of related experience or M.Tech or equivalent and a minimum of 6 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys s Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills The Team You ll Be A Part Of: You will be part of a dedicated product validation team for Formality, working closely with R&D, product engineering and field applications engineering teams. Your team focuses on ensuring the high quality of new releases and features of Formality tool, enabling customers to accurately and timely validate their high-performance designs. Together, you will tackle complex technical challenges and drive continuous improvement in our product validation processes. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ======================== At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

An enthusiastic and detail-oriented individual with a passion for electronics and hardware testing. You have a diploma or bachelors degree in Electrical or Electronics Engineering and are eager to apply your knowledge in a dynamic lab environment. Your hands-on experience with lab instruments and your understanding of high-speed interfaces like Ethernet and PCIe make you a strong candidate for this role. You are meticulous in your work, ensuring that all lab activities are executed seamlessly. You enjoy troubleshooting and solving technical challenges, and you are comfortable working in a fast-paced, collaborative environment. What You ll Be Doing: Configure, calibrate, and maintain test equipment such as oscilloscopes, logic analyzers, signal generators, and power supplies. Assist in assembling and setting up test benches for silicon validation, ensuring signal integrity and proper connectivity. Support high-speed interface testing, particularly for PCIe, Ethernet, and other serial communication protocols. Perform PCB rework, soldering, and desoldering of surface-mount (SMD) and through-hole components. Work closely with validation engineers to execute pre-silicon and post-silicon validation tests. Capture, analyze, and document test data using lab measurement tools. Troubleshoot hardware issues, connectivity problems, and signal integrity challenges related to PCIe and Ethernet interfaces. Maintain detailed logs of test results, test setups, and debugging activities. Assist in generating test reports and summaries for engineering teams. Ensure compliance with ESD protection guidelines and ISO standards for lab operations. Organize lab space and maintain an inventory of test equipment, components, and accessories. Ensure lab equipment is functional and regularly serviced for optimal performance. Follow standard operating procedures (SOPs) for equipment handling and storage. Manage procurement requests for test equipment and consumables, coordinating with vendors and internal teams. The Impact You Will Have: Ensure the seamless execution of validation activities, contributing to the high-quality standards of our products. Support the development and validation of cutting-edge silicon technologies, pushing the boundaries of innovation. Maintain a well-organized and efficient lab environment, enabling the engineering team to focus on core development tasks. Provide critical data and insights through meticulous documentation and reporting, aiding in informed decision-making. Enhance the reliability and performance of our hardware through thorough testing and troubleshooting. Contribute to the continuous improvement of lab operations and processes, ensuring compliance with industry standards. What You ll Need: Bachelors degree (B.Tech/B.E.) in Electrical, Electronics. 2 years of experience in a semiconductor validation or hardware testing lab. Hands-on experience with electronic lab equipment (oscilloscopes, multimeters, power analyzers, etc.). Basic understanding of PCB schematics, signal integrity, and electrical debugging. Familiarity with high-speed interfaces, including Ethernet and PCIe. Working knowledge of Python, MATLAB, and C for test automation is a plus. Strong problem-solving skills and attention to detail.

You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working closely with cross-functional teams to solve complex technical challenges. Your expertise in Synopsys PrimeTime and related technologies allows you to diagnose issues and propose innovative solutions that enhance product quality. You are self-motivated, with a proven track record of executing comprehensive validation plans and delivering high-quality results. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python enable you to streamline processes and improve efficiency. You are committed to continuous learning and staying up-to-date with the latest industry trends and advancements. What You ll Be Doing: Execute and lead product validation of Synopsyss PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases. Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to reduce customer incoming thereby improving product quality. Collaborate with cross-functional teams such as R&D, Product Engineering, Field and Customers, recommend improvements in implementation and validation. Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues and propose solutions to ensure quality and readiness of the product/solution for customer deployment. Demonstrate a high level of attention to detail and accuracy in all tasks. Perform risk assessments and develop mitigation strategies to address potential product validation issues. Analyze validation data to identify trends, discrepancies and areas for improvement. Prepare detailed validation reports to present to multi-functional teams and management. The Impact You Will Have: Ensure the high quality and reliability of Synopsyss PrimeTime tool, contributing to its success in the market. Enhance customer satisfaction by proactively identifying and addressing potential issues before they impact users. Collaborate with R&D and Product Engineering teams to drive continuous improvements in product design and functionality. Provide valuable insights and recommendations that influence the development and validation of future product releases. Contribute to the overall success of Synopsys by ensuring that our tools meet the highest standards of performance and reliability. Support the deployment of cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. What You ll Need: Deep domain knowledge in Static Timing Analysis. BSEE or equivalent and a minimum of 2 years of related experience or MSEE or equivalent and a minimum of 1 year of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, Extraction, power, SDC constraints, advanced OCV concepts, derates, PBA timing, distributes, hierarchical STA flows, and/or physical design closure. Exceptional debugging skills. Proficient in software and scripting skills (Perl, Tcl, Python). Detail-oriented with a focus on maintaining high standards of product quality. Who You Are: Collaborative team player with excellent communication skills. Analytical thinker with a problem-solving mindset. Proactive and self-motivated individual. Adaptable and flexible in a fast-paced environment. Strong attention to detail and accuracy.

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL Cache. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification.

Characterizing and modeling standard cells for various technologies and foundries. Conducting quality analysis of characterized liberty and Verilog models in terms of timing, power, and functionality. Validating characterization and simulation tool versions including PrimeLib, Hspice, PrimeSim, and Finesim. Providing daily status updates on project progress. Ensuring timely and quality releases of projects. Collaborating with cross-functional teams to enhance design and verification processes. The Impact You Will Have: Enhancing the accuracy and efficiency of standard cell models across various technologies. Improving the quality and reliability of characterized models in terms of timing, power, and functionality. Streamlining validation processes for characterization and simulation tools, ensuring robust tool versions. Contributing to the timely delivery of high-quality releases, meeting project deadlines and standards. Supporting technological innovation through meticulous analysis and validation. Fostering collaboration and knowledge sharing within cross-functional teams for continuous improvement. What You ll Need: 5 Years of experience in Standard Cell Characterization Thorough knowledge of MOSFET and FINFET technologies. Experience with PrimeLib, Hspice, PrimeSim, and Finesim tools. Strong analytical skills for quality analysis of characterized models. Proficiency in characterizing and modeling standard cells for various technologies. Excellent communication skills for providing daily status updates and collaborating with teams. Who You Are: A detail-oriented professional with a strong analytical mindset. A proactive communicator, able to provide clear and concise updates. A collaborative team player, ready to work with cross-functional teams. A dedicated individual committed to delivering high-quality work on time. An innovative thinker, always looking for ways to improve processes and outcomes.

Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally distributed teams Drive research and development initiatives to stay ahead in the industry Support Synopsys mission to lead in the Era of Pervasive Intelligence What You ll Need: Bachelors or Masters degree in Electrical or Electronics Engineering Minimum of 5 years of relevant experience Proficient in Transmission line theory and time/frequency-domain analysis Experienced with SPICE and familiar with 3D field solvers Conversant with working of DDR and PCIe/Ethernet interfaces Good verbal and written English communication skills Experience in scripting languages such as Python and TCL is a plus Familiarity with both Windows and Linux operating system

We are seeking a highly motivated Product Engineer who is passionate about advancing technology and solving complex design challenges. You are innovative, dependable, and have a strong technical background in transistor-level analysis. With a minimum of 5 years of hands-on experience, you possess exceptional expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. You have a deep understanding of static timing concepts and CMOS engineering fundamentals, coupled with proficiency in TCL or other scripting languages. Your excellent communication and social skills enable you to collaborate effectively with cross-functional teams, including R&D, Field AEs, Sales, and Marketing. You thrive in a dynamic environment, driving new products and features that exceed customer expectations and contribute to the success of Synopsys. What You ll Be Doing: Drive new products and new product features that exceed customer needs. Work with R&D to enable timely implementation of new products and features, and important bug fixes. Provide consultation to prospective users and/or product capability assessment and validation. Provide tool trainings to customers and Field AEs. Provide technical expertise to sales staff through sales presentations and product demonstrations. Assist the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. The Impact You Will Have: Influence technology and solution roadmaps through collaboration with R&D. Ensure overall consistency of end-to-end design and analysis flow to meet customer needs. Drive new tool evaluations and help customers with the adoption and continuous usage of our tools. Enable Chip Design customers to achieve optimal Timing, Power, and Characterization goals. Enhance predictability and productivity for designers through advanced tool features. Identify and resolve design issues early-on, minimizing costly late-stage silicon problems. What You ll Need: BS degree in Electrical Engineering or related field. Minimum of 5 years of recent hands-on experience in transistor-level analysis. Expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. Proficiency in static timing concepts and CMOS engineering fundamentals. Knowledge of TCL and/or other scripting languages. Who You Are: Innovative and motivated. Dependable and detail-oriented. Excellent communicator and collaborator. Proactive problem solver. Adaptable and eager to learn

Review SerDes standards and architecture documents to develop analog sub-block specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Required Qualifications: Bachelor with 4 years experience or MSEE (or PhD) with 2 years experience in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

As an experienced Verification Engineer, you are passionate about ensuring the highest standards of quality in complex system designs. With over a decade of experience in IP verification, you bring a deep understanding of verification methodologies and the intricacies of hardware design. You are adept at designing self-checking test benches using modern verification techniques, and you excel in developing verification components such as bus functional models, monitors, and behavioral models. Your expertise in implementing functional coverage and assertions using System Verilog is unmatched. You are a problem-solver who thrives in debugging simulation failures and analyzing functional coverage results. Your strong Verilog coding skills, combined with your prowess in C/C++ or Python scripting, make you a valuable asset to any team. You are a fast learner, comfortable and confident interacting with architects, and you possess excellent written and verbal communication skills. What You ll Be Doing: Designing and implementing self-checking test benches using modern verification techniques. Developing verification components such as bus functional models, monitors, and behavioral models. Implementing functional coverage and assertions using System Verilog. Creating and executing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures to identify root causes. Evaluating functional coverage results to ensure thorough verification. The Impact You Will Have: Ensuring the highest quality of IP verification, contributing to the reliability and performance of cutting-edge technology. Enhancing the efficiency of the verification process through innovative test bench designs. Contributing to the development of high-performance silicon chips that power a wide range of applications. Supporting the continuous improvement of verification methodologies and best practices. Collaborating with cross-functional teams to achieve project milestones and deliverables. Mentoring and guiding junior engineers, fostering a culture of knowledge sharing and continuous learning. What You ll Need: B.Tech/M.Tech with a minimum of 10+ years experience in IP verification. Proficiency in Verilog and System Verilog for test bench development. Experience with object-oriented verification languages like SV, UVM. Strong debugging skills and experience with industry-standard simulation tools such as Synopsys VCS, Verdi. Knowledge of FPGA architectures and experience in DDR IP verification. Who You Are: A fast learner with the ability to quickly adapt to new technologies and methodologies. An excellent communicator with strong written and verbal communication skills. A team player who collaborates effectively with cross-functional teams. An analytical thinker with strong problem-solving skills. A mentor who enjoys sharing knowledge and guiding junior engineers.

Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis

Designing, implementing, and optimizing CI/CD pipelines for cloud and hybrid environments. Integrating AI-driven pipeline automation for self-healing deployments and predictive troubleshooting. Leveraging GitOps (ArgoCD, Flux, Tekton) for declarative infrastructure management. Implementing progressive delivery strategies (Canary, Blue-Green, Feature Flags). Containerizing applications using Docker & Kubernetes (EKS, AKS, GKE, OpenShift, or on-prem clusters). Optimizing service orchestration and networking with service meshes (Istio, Linkerd, Consul). Implementing AI-enhanced observability for containerized services using AIOps-based monitoring. Automating provisioning with Terraform, CloudFormation, Pulumi, or CDK. Supporting and optimizing distributed computing workloads, including Apache Spark, Flink, or Ray. Using GenAI-driven copilots for DevOps automation, including scripting, deployment verification, and infra recommendations. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD pipelines and deployments. Driving the adoption of AI-driven automation to reduce downtime and improve system resilience. Enabling seamless application portability across on-prem and cloud environments. Implementing advanced observability solutions to proactively detect and resolve issues. Optimizing resource allocation and job scheduling for distributed processing workloads. Contributing to the development of intelligent DevOps solutions that support both traditional and AI-driven workloads. What You ll Need: 5+ years of experience in DevOps, Cloud Engineering, or SRE. Hands-on expertise with CI/CD pipelines (Jenkins, GitHub Actions, GitLab CI, ArgoCD, Tekton, etc.). Strong experience with Kubernetes, container orchestration, and service meshes. Proficiency in Terraform, CloudFormation, Pulumi, or Infrastructure as Code (IaC) tools. Experience working in hybrid cloud environments (AWS, Azure, GCP, on-prem). Strong scripting skills in Python, Bash, or Go. Knowledge of distributed data processing frameworks (Spark, Flink, Ray, or similar)

An experienced and passionate Layout Design Sr Engineer with a strong background in Analog and Mixed Signal Circuit Layout. You possess a deep understanding of semiconductor device physics and have hands-on experience in EDA tools for custom mixed signal layout flows. Your expertise in CMOS and FINFET technologies, coupled with your knowledge of CMOS fabrication technology, equips you to handle deep sub-micron effects and their impact on layout. You are self-directed, detail-oriented, and have excellent problem-solving and communication skills. Your enthusiasm for learning and exploring new layout techniques drives you to innovate and excel in your role. What You ll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You ll Need: Bachelors or masters degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus. Who You Are: Self-directed and detail-oriented. Excellent problem-solving skills. Strong communication skills. Passionate about learning and exploring new layout techniques

Enable, support, and debug transistor-level flows and processes. Design, develop, troubleshoot, and debug software tools and flows for the development of integrated circuits. Support a global design team, debug CAD issues, interface with foundries, configure the CAD environment, and design flows. Develop routines and utility programs to aid in the design of integrated circuits. Build productive internal and external working relationships. Requirements: A relevant degree in electronic/microelectronic engineering. 5+ years of relevant experience. Strong desire to learn and explore new technologies, demonstrating good analysis and problem-solving skills. Ability to exercise judgment within defined procedures and practices to determine appropriate action. Good knowledge of hardware integrated circuits. UNIX/Linux user knowledge. Proficiency with at least one programming language. Proficiency with scripting languages to automate processes. Good English communication skills. Capability to produce adequate technical documentation. Preferred Qualifications: Experience with the VLSI domain, including familiarity with DRC/LVS extraction, simulation, and EMIR. Experience with Cadence, Custom Designer EDA tools. Experience in data management and job scheduling tools like LSF/GRID Engine. Experience in Python, TCL, or Shell scripting. IC design experience (analog or digital).

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Review SerDes standards and architecture documents to develop analog sub-block specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Required Qualifications: Bachelor with 4 years experience or MSEE (or PhD) with 2 years experience in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Develop and maintain circuit design methodology flows and documentation. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Required Qualifications: Bachelor with 2 years experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits like bandgap references, voltage regulators. Detailed design experience with high custom logic design Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

"> Search Jobs Find Jobs For Where Search Jobs Technical Writer Hyderabad, Telangana, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10602 Date posted 04/17/2025 Share this job Email LinkedIn X Facebook Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Energetic, experienced, and organized, you are a writer who thrives in a vibrant environment and is passionate about cutting-edge technology. You have a knack for turning complex technical information into clear, concise, and user-friendly documentation. With a strong background in technical writing within the software or hardware industry, you bring a blend of creativity and precision to your work. You are a team player who can also work independently, and you take pride in delivering high-quality content on time. Your excellent communication and interpersonal skills enable you to collaborate effectively with engineers and other stakeholders. You are always eager to learn and adapt to new technologies, ensuring that your documentation remains relevant and up-to-date. If you care about doing a good job, about details, and about contributing to a dynamic team, Synopsys is the place for you. What You ll Be Doing: Planning, organizing, writing, and editing a variety of customer documentation. Collaborating with engineers to understand product functionalitie s and features. Creating user manuals, reference guides, and online help content in various formats. Ensuring documentation is accurate, clear, and comprehensive. Maintaining and updating existing documentation to reflect product updates. Utilizing authoring tools such as FrameMaker and Oxygen to produce high-quality content. The Impact You Will Have: Empower customers to effectively use and optimize Synopsys products. Enhance user experience through clear and accessible documentation. Support product adoption and customer satisfaction. Contribute to the success of product releases with timely and accurate documentation. Facilitate better communication and understanding between customers and the engineering team. Help maintain Synopsys reputation as a leader in semiconductor IP solutions. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering disciplines. Other technical disciplines considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solvin g skills with strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Excellent English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player with the ability to work independently. Detail-oriente d and committed to delivering high-quality work. Proactive and able to take ownership of projects with minimal supervision. The Team You ll Be A Part Of: You will be part of a dynamic and experienced Technical Publications team that works closely with world-class engineers to create essential customer documentation. Our team is committed to empowering customers worldwide with comprehensive and user-friendly content that enhances their experience with Synopsys products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs DevOps Staff Engineer Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10097 Date posted 03/19/2025 Share this job Email LinkedIn X Facebook We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a proactive and experienced Staff DevOps Engineer with a passion for cutting-edge technologies. You excel in CI/CD, automated testing, and deployment across the Software Development Life Cycle. Your background includes strong cloud and containerization skills, scripting, and a knack for innovation and automation. You hold a relevant degree and certifications, bringing at least 5 years of experience in software development and DevOps. What You ll Be Doing: Driving CI/CD and automation efforts. Implementing frameworks for on-prem and cloud environments. Building platforms for application and infrastructure management. Defining development pipelines. Working within Agile frameworks. Monitoring DevOps metrics and dashboards. Mentoring and overseeing team members. The Impact You Will Have: Enabling faster, reliable software releases. Enhancing management of applications and infrastructure. Contributing to making Synopsys products cloud-ready. Driving organizational innovation and automation. Aligning development flows with operational goals. Improving software delivery processes. What You ll Need: Relevant Bachelors or Masters degree. 5+ years of software development/deployment experience. Cloud certifications (AWS, GCP, Azure). 3-5 years of DevOps experience. Experience with Linux and Windows. Scripting skills (Bash, Python, Perl). CI/CD tools proficiency (GitHub, GitLab, Bitbucket). Containerization and orchestration experience (Docker, K8s). Ansible and Jenkins automation skills. Proficiency with DevOps tools (JIRA, Confluence, Jenkins). Who You Are: You are a creative problem-solver with strong analytical skills. You communicate effectively, lead teams, and advocate for continuous improvement in CI/CD processes. You are experienced in diverse technical environments and are a mentor to your peers. The Team You ll Be A Part Of: Join the central software engineering organization at Synopsys, contributing to our digital transformation and cloud-readiness efforts. Collaborate with cross-functional teams to drive CI/CD, automation, and innovative software delivery processes. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Detailed information about salary and benefits will be provided during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs ASIC DFT, Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 5945 Remote Eligible No Date Posted 04/11/2024 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a driven and detail-oriented individual with a passion for cutting-edge technology and continuous learning. With 0-1 years of related experience, you possess a sufficient understanding of DFT architectures and methodologies, including Scan insertion, ATPG, JTAG, and SIMS. You have moderate experience in generating scan patterns and coverage statistics for various fault models like stuck-at, IDDQ, transition faults, and path delay. Your experience in scan stuck-at and at-speed coverage exploration, simulation, and debug is commendable. Familiarity with state-of-the-art EDA tools for DFT, design, and verification is a plus. Additionally, you have some knowledge of STA for DFT mode timing constraint development and exploration. Your debugging skills and demonstrated experiences in Perl/TCL/Python scripting are an advantage. You are an excellent communicator and can effectively work with cross-functional teams across geographies. Design experience in MBIST, LBIST, and Analog DFT is an added advantage. You value inclusion and diversity and are committed to contributing to a collaborative and innovative work environment. What You ll Be Doing: Implementing DFT architectures and methodologies, including Scan insertion, ATPG, JTAG, and SIMS. Generating scan patterns and coverage statistics for various fault models. Exploring, simulating, and debugging scan stuck-at and at-speed coverage. Utilizing state-of-the-art EDA tools for DFT, design, and verification. Developing and exploring STA for DFT mode timing constraints. Collaborating with cross-functional teams across geographies to achieve project goals. The Impact You Will Have: Enhancing the reliability and quality of our high-performance silicon chips through robust DFT methodologies. Contributing to the efficiency of our chip design and verification processes. Supporting the continuous innovation of our technology and products. Ensuring seamless integration of DFT in our chip design workflows. Improving fault detection and coverage, thereby reducing time-to-market for our products. Fostering a collaborative and inclusive work environment that drives technological advancements. What You ll Need: 0-3 years of related experience in DFT architectures and methodologies. Moderate experience in generating scan patterns and coverage statistics for various fault models. Experience in scan stuck-at and at-speed coverage exploration, simulation, and debug. Familiarity with state-of-the-art EDA tools for DFT, design, and verification. Basic knowledge of STA for DFT mode timing constraint development and exploration. Who You Are: Excellent communicator with the ability to work effectively with cross-functional teams. Detail-oriented and driven by a passion for technology and continuous learning. Strong debugging skills and experience in scripting languages like Perl, TCL, and Python. Committed to fostering an inclusive and diverse work environment. Adaptable and eager to take on new challenges and responsibilities. The Team You ll Be A Part Of: You will join a dynamic and innovative team focused on developing and implementing cutting-edge DFT methodologies to enhance the reliability and performance of our silicon chips. The team collaborates closely with cross-functional groups across geographies to drive technological advancements and achieve project goals. Together, we are committed to continuous learning, innovation, and fostering an inclusive work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.

Lumenci is a legal tech startup founded by a group of IIT alumni in the US. Lumenci s mission is to transform the legal and intellectual property industry in US Europe with groundbreaking products and services. We are currently looking to build an exceptionally strong technical team in Gurgaon, India, to help us deliver high-quality products and services to our clients. Lumenci is looking for self-driven, gritty, technology enthusiasts. If you are curious about technology, enjoy working in a high-growth startup, are hands-on with gadgets, and keep up with the next big thing in Tech-you might be a great fit. Responsibilities and Duties Provide technology consulting services to law firms and corporates. Understand underlying technologies to analyze patent portfolios and help solve clients core technical queries. Lead teams conducting research analysis, including but not limited to technology research. Experience with IP matters (infringement analysis, EOUs, prior art searches, landscaping, etc.). Proficiency in Semiconductor technologies including Microprocessors, Microcontrollers, Memory, SoC, FPGA, ASIC, and VLSI. Strong understanding of semiconductor fabrication, circuit design, and electronic components. Explain complex technology matters to non-technical audiences. Handle calls with US-based clients who include Industry Experts, Corporate Counsel, CEOs, Startup founders, IP litigators, etc. Work with product teams to guide the development testing of Lumenci s technology platforms. Showcase technology and IP thought leadership via blogs and research reports. Collaborate across the organization in-person and with virtual, global teams. Establish and cultivate relationships internally and externally. Expected Competencies and Skill Excellent verbal and written communication skills. Expert level proficiency in technical research. Strong attention to detail. Good in managing client expectations. Customer-oriented approach. Problem-solving aptitude. Ability to think critically, learn fast and work with minimal supervision under tight deadlines. Entrepreneurial and go-getter attitude. Education and Experience BTech/ M.Tech in Electronics, Communications, or related fields from premier colleges such as IITs, BITS, and NITs. 4-6 years of experience in relevant Tech industry e.g. Semiconductor, Embedded Systems, Chip Design, VLSI, and EDA tools. Benefits Performance-driven compensation package. Rapid career growth. An ideal candidate would share our way of working: Solve for the Customer: Lumenci is a customer-first company, with the focus to create a long-term relationship with our clients. Customer here includes internal employees and candidates who are part of the recruitment process. Quality, Ownership, and Accountability: We are passionate about results and take full ownership of our work. We are performance-oriented and have a drive for excellence. Collaboration: We encourage collaboration over competition, work in small teams, and believe that teams do better than individuals. Growth Mindset: We are adaptable to changing requirements and needs of a dynamic high-growth company. We encourage each other to take diverse initiatives and develop new competencies. About Lumenci: Lumenci is the technology industry s most strategic patent monetization partner. We work with the world s top technology companies, law firms, inventors, and start-ups to find the value in their inventions and help them pursue and defend that value throughout the ideation to monetization lifecycle. We help clients convert innovation into patent portfolios and identify their best monetization opportunities. We work with a wide variety of technologies including hardware and software, telecom, networking, and biotech technologies. Lumenci combines technology domain expertise with strategic industry connections to guide towards the best route to ROI. From ideation to monetization -- we illuminate the way.

Skills :. Experience in project management, with a focus on the front-end stages of semiconductor chip design, technical background in digital design, verification, and synthesis,EDA Tools Required Candidate profile Notice Period: immediate Education: Masters in VLSI design from reputed universities like IIT/NIT with background in Bachelors in Electronics and Communication, or a related field