431 Chip Design Jobs - Page 4

Engaging directly with Synopsys customers to understand verification needs and define project scope and activities. Developing and implementing system design solutions using Synopsys EDA tools and IP. Leading a team of engineers in executing pre-silicon verification activities for IPs and subsystems. Anticipating technical challenges and risks, and formulating effective resolution and mitigation plans. Mentoring and coaching team members to enhance their technical capabilities and performance. Reviewing results and reports to provide constructive feedback, driving continuous improvement in quality. Reporting project status to management and recommending solutions to address execution issues....

Engage with Synopsys customers to understand verification needs and define project scopes and deliverables. Lead and mentor a team of engineers to execute pre-silicon verification activities on complex IPs and subsystems. Develop verification plans, resource requirements, and risk mitigation strategies to ensure successful project execution. Review results and reports, providing continuous feedback to enhance quality and efficiency. Report status to management, offering insights and solutions for potential project challenges. Collaborate with architects, designers, and pre/post-silicon teams to achieve verification goals. Ramp-up on new verification tools and methodologies, leveraging Synops...

Engage with Synopsys customers to understand verification needs and define project scopes and deliverables. Lead and mentor a team of engineers to execute pre-silicon verification activities on complex IPs and subsystems. Develop verification plans, resource requirements, and risk mitigation strategies to ensure successful project execution. Review results and reports, providing continuous feedback to enhance quality and efficiency. Report status to management, offering insights and solutions for potential project challenges. Collaborate with architects, designers, and pre/post-silicon teams to achieve verification goals. Ramp-up on new verification tools and methodologies, leveraging Synops...

Designing, developing, and testing bare metal firmware for high-speed mixed-signal IP blocks, focusing on NRZ and PAM-based SerDes products. Collaborating closely with digital and mixed-signal design teams to define specifications, implement RTL designs, and validate performance on prototype test-chips. Executing structured firmware development, verification, and documentation processes to ensure robust and maintainable solutions. Driving projects from initial concept to successful completion, including functional and performance testing on silicon. Interfacing with cross-functional groups and customer support teams to resolve technical issues and deliver exceptional support. Utilizing scrip...

Conceptualizin g, designing, and productizing state-of-the-a rt circuit components for SLM monitors realized through ASIC design flow. Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. Developing statistical simulation methodologies and collaborating with the layout team to achieve optimal design solutions. Characterizing designed custom cells and deploying new circuits into test chips for post-silicon characterizati on. Creating new cells and updating existing ones through collaboration with architects and Physical Design engineers. Conducting pre and post-layout simulations and characterizati ons across various design corners to ...

Designing and developing comprehensive verification test plans and infrastructure based on design specifications and customer requirements. Implementing and analyzing SystemVerilog assertions and coverage metrics (code, toggle, functional) to ensure design correctness. Leading verification activities, mentoring junior engineers, and assisting in debugging complex issues. Collaborating closely with architects, designers, and pre & post silicon verification teams to achieve project goals. Adhering to rigorous quality standards and best practices in test and verification processes. Rapidly ramping up on new verification tools and methodologies using Synopsys products to enable customer success....

Designing and developing comprehensive verification test plans and infrastructure based on design specifications and customer requirements. Implementing and analyzing SystemVerilog assertions and coverage metrics (code, toggle, functional) to ensure design correctness. Leading verification activities, mentoring junior engineers, and assisting in debugging complex issues. Collaborating closely with architects, designers, and pre & post silicon verification teams to achieve project goals. Adhering to rigorous quality standards and best practices in test and verification processes. Rapidly ramping up on new verification tools and methodologies using Synopsys products to enable customer success....

Data/problem analysis Research the solution space Develop concepts Prototype and validate concepts Specify software requirements Software/algorithm development (productization/programming) Minimum Qualifications Masters Level Degree and 0 years related work experience; Bachelors Level Degree and related work experience of 2 years

Design and develop machine learning software solutions for semiconductor device and thin film metrology Work with both internal and external customers to define requirements for these software solutions Build machine learning-based software solutions Optimize algorithms and prototypical solutions for efficient implementation Design, develop, implement, oversee, and adapt API Extend prototypes into fully functional, polished solutions ready for internal and/or external use Implement solutions in Python with TensorFlow Write comprehensive unit tests and provide technical support during alpha and beta testing Document the design and implementation of the software solutions, and give presentatio...

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog /DFT Analog/PD Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 4 to 15 years industry/teaching experience Good communication & presentation skill

As a Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secur...

Designing and developing physical layouts for high-speed analog and mixed-signal IP blocks including SerDes, RX, TX, PLL, and custom logic paths. Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs. Utilizing advanced CAD tools (Custom Designer, Cadence Virtuoso, Calibre, ICV, STAR-RXCT) for layout creation, verification, and debugging. Executing deep submicron layout techniques, including floor-planning, ESD/latchup mitigation, and process technology adaptation. Implementing and verifying layout flows such as LEF generation, top-level verification, DRC/LVS/LPE, and power routing with EM/IR considerations. Providing technical l...

Designing and implementing high-performance DDR I/O analog circuits for advanced SoC applications. Collaborating with digital and mixed-signal teams to ensure seamless integration of analog IP blocks. Executing circuit design tasks with a focus on product quality, efficiency, and adherence to project timelines. Conducting simulations, verification, and layout reviews to optimize circuit performance and robustness. Interpreting and applying JEDEC DDR interface standards, timing, and ODT requirements in your designs. Participating in design reviews and providing technical guidance to junior engineers and peers. Documenting design methodologies, results, and best practices for internal knowledg...

Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC...

Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-stand ard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturabil ity and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improveme...

Leads and manages silicon design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP, sub-system, SoC, and/or discrete chip. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards. Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements. Works to continuously to improve silicon development processes and architecture definition across areas of silicon design. Oversees and reviews design verification test results, data analysis, issue track...

As a System-on-Chip Design Engineer (Analog IP/IC) specializing in Semiconductor Chip Design, you will play a crucial role in leading and coordinating the execution of analog and mixed-signal integrated circuit development projects. With 8-12 years of experience, you will be part of a Japanese multinational client's Semiconductor development center based in Bangalore. Your responsibilities will involve designing high-performance analog circuits, ensuring precision and reliability in semiconductor designs. Key Responsibilities: - Designing analog/mixed-signal blocks such as ADC/DAC, PLL, LDO/DCDC, IO, Motor & Gate Drivers. - Running MATLAB modeling, circuit simulations, and post-layout analys...

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required educ...

Roles: As the Senior CAD Infrastructure Engineer , you will be responsible for architecting, designing, implementing, deploying and managing a scalable, high-performance CAD infrastructure that supports complex semiconductor design workflows for our various chip design teams. As a key technical leader of the team, you will collaborate with R&D Functional Design teams, IT, High-Performance Computing (HPC) datacenter operation team, EDA vendors and other relevant cross-functional groups to ensure the CAD environment is optimized for performance, scalability, reliability, and the robust infrastructure solutions meet the diverse chip development needs. You will drive the roadmap for CAD compute ...

As a part of Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical implementation, Timing closure an...

As a part of in Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. Responsibilities: Timing analysis and closure responsibilities at SoC level as well as block/subsystem level Review of timing QOR at every execution milestones and supervising to meet required guideline for smoother closure ECO planning, generation and tracking to closure by collabor...

As a part of in Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM Designs. Analyze design timing, area and power to help improve the quality of ARM Design. Optimize design, flow and methodologies to achieve best in class PPAT working with...

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to imp...

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to imp...

Company Overview Group/Division Job Description/Preferred Qualifications Algo engineer Minimum Qualifications Doctorate (Academic) Degree and 0 years related work experience; Masters Level Degree and related work experience of 3 years; Bachelors Level Degree and related work experience of 5 years