187 Chip Design Jobs - Page 2

Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.

You are a highly experienced and motivated professional with a solid background in SoC RTL Design . With over 12 years of experience , you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development . You possess a deep understanding of design concepts, ASIC flows, and stakeholder management . Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints . You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables . Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You'll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities . Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 12+ years of experience in SoC RTL Design . Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain.

You are an experienced and highly motivated professional with a strong background in analog and mixed-signal (A&MS) layout design . You thrive in a collaborative environment and possess a keen eye for detail and design integrity. Your technical expertise in using industry-standard EDA tools , coupled with your problem-solving abilities, makes you a valuable asset to any team. You have a deep understanding of semiconductor process technologies and their impact on layout design, and you are always eager to stay updated with the latest industry trends and advancements. With exceptional communication and interpersonal skills, you work effectively in team-oriented environments and contribute positively to the collective success. What You'll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Enhance the reliability and performance of our PVT sensor IPs through meticulous layout design. Ensure manufacturability and integrity of designs, avoiding costly errors in production. Contribute to the development of cutting-edge technologies in the semiconductor industry. Support the continuous improvement of design methodologies and best practices. Facilitate the integration of our IPs into SOC subsystems, aiding in the creation of high-performance silicon chips. Drive the technological innovations that keep Synopsys at the forefront of the industry. What You'll Need: Bachelor's or master's degree in electrical engineering or a related field. 3+ years of experience in A&MS layout design for integrated circuits. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura.

Design and develop software for interface IP systems Perform Device level and System level, validation and debug, in post-silicon Software Development for new validation methodologies Customer interface to capture requirement and post release support Maximize software productivity and faster time to knowledge Qualifications: Qualification: B.Tech in ECE/CS or equivalent with 4+ year of relevant experience ECE background with experience is software is preferred Skills: Excellent programming and testing skills using C/C++ Experience with embedded or resource-constrained environments Development experience on Unix, Linux and Windows Ability to pick up new flow, learn on the Job MATLAB & PYTHON programming exposure is plus Excellent verbal and written communication skill

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality, and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer.

You're an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership. You're eager to learn and contribute to the development of state-of-the-art PVT IP sensors that are integral to the silicon lifecycle monitoring process. You possess a mindset geared towards meticulous IP debug and documentation, ensuring the highest standards of product development and performance. What You'll Be Doing: Serving as the single point of contact for post-silicon debug activities. Enabling Product Requirement Documents (PRDs). Working to enable IP as a product development platform. Handling hands-on post-silicon test setups. Collaborating on top-level physical design, board-level, and package-level designs. Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: Driving the successful development and deployment of PVT IP sensors. Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. Ensuring high-quality product development through meticulous testing and debugging. Contributing to continuous innovation in chip design and software security. Supporting Synopsys leadership in the market for PVT IP developments. Empowering the creation of high-performance silicon chips used in various advanced technologies. What You'll Need: Hands-on experience in post-silicon test setups. Sound knowledge of Digital/AMS chip design and post-silicon debug. BS or MS degree in Electrical Engineering with 3+ years of experience. Understanding of top-level physical design, board-level, and package-level designs. Expertise in RTL development and physical design.

Contribute to the development and enhancement of layout design methodologies and best practices. Work closely with different function design leaders to understand/enhance processes and help to enhance methodology. Collaborate with internal infrastructure teams on compute grid, storage management, and job scheduling architecture, efficiency, maintenance, and forecasting. Understanding CAD infrastructure and methodology will help to set up project environments. Contribute to enhancing quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Stay updated with the latest industry trends and advancements in A&MS layout design. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views will add value to this position. Writing RTL Code and TCL is a good addition. The Impact You Will Have: Enhance layout design methodologies and best practices, contributing to the overall quality and efficiency of the design process. Improve project forecasting capabilities by leveraging advanced monitoring and scheduling techniques. Boost productivity across ASIC design cycles through the development and automation of internal tools. Ensure design integrity and manufacturability through meticulous physical verification and design rule checks. Stay at the forefront of industry advancements, bringing the latest trends and technologies into Synopsys design practices. Collaborate effectively with cross-functional teams, driving innovation and continuous improvement in design methodologies. What You ll Need: Bachelor s or master s degree in engineering or a related field. 2 to 3+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

You are an experienced ASIC Digital Design Engineer with a deep understanding of interface protocols such as USB2/3/3.1, PCIe Gen1/2/3/4/5/6, Ethernet, and JESD204B. With a solid background in SERDES/PHY/Controller IP specification and compliance validation, you thrive in dynamic environments where your expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM) is highly valued. You are passionate about delivering high-quality RTL and simulation models, and you excel in developing and reviewing verification plans and environments. Your proactive approach to problem-solving, coupled with your ability to support customers during silicon bring-up and debug phases, makes you an invaluable asset to any team. Your technical prowess is matched by your excellent communication skills, enabling you to effectively collaborate and influence across departments and with external partners. What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing the quality and reliability of our silicon solutions for customers. Facilitating smooth customer adoption and integration of our IPs. Contributing to successful silicon bring-up and debugging efforts. Showcasing our technological advancements at industry events. Driving innovation and excellence in digital design and verification processes. What You'll Need: Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Experience with SERDES/PHY/Controller IP specification and compliance validation. Strong background in developing and reviewing verification plans and environments. Ability to deliver high-quality RTL and simulation models to customers.

Collaborating with cross-functional teams to define project requirements, scope, and objectives. Developing detailed project plans, including timelines, resource allocation, and risk management strategies. Monitoring project progress and performance, identifying potential issues, and implementing corrective actions as needed. Communicating project status, updates, and milestones to stakeholders, ensuring transparency and alignment. Representing R&D on customer relationships, tracking execution to plan, aligning with senior leadership of team on mitigation and escalation management Mentoring and guiding team members, fostering a collaborative and innovative work environment. The Impact You Will Have: Driving the successful execution of engineering projects, contributing to Synopsys reputation for excellence and innovation. Enhancing the efficiency and effectiveness of project management processes, leading to improved project outcomes. Facilitating cross-functional collaboration, ensuring that all teams are working towards common goals. Providing leadership and mentorship to team members, fostering their professional growth and development. Ensuring that projects are delivered on time, within scope, and within budget, contributing to the overall success of the organization. Identifying opportunities for process improvements and implementing best practices to enhance project delivery.

Collaborating with R&D and Application Engineers to define and validate the latest hybrid emulation technologies. Engaging in field discussions with customers to provide expert insights and advanced debugging support. Participating in strategic bring-ups to ensure successful implementation of new technologies. Conducting product validation to ensure the highest quality and performance standards are met. Creating and maintaining comprehensive documentation for our products. Developing and delivering training sessions to enhance the knowledge and skills of internal teams and customers. The Impact You Will Have: Driving the adoption and usability of our hybrid emulation technologies among customers. Providing valuable technical insights that influence the direction of product development. Ensuring the successful deployment of new technologies through strategic bring-ups and customer support. Maintaining high standards of product quality and performance through rigorous validation processes. Enhancing the technical knowledge and capabilities of internal teams and customers through effective training. Contributing to the continuous improvement and innovation of our products. What You ll Need: Extensive experience in hybrid emulation and related technologies. Strong technical expertise in product validation, advanced debugging, and strategic bring-ups. Proficiency in creating and maintaining comprehensive product documentation. Excellent communication and presentation skills for delivering effective training sessions. Ability to work collaboratively with R&D and other Application Engineers.

Providing technical support and expertise to global customers using Synopsys Implementation products. Engaging in specific flagship projects and providing enabling solutions in all parts of the design implementation flow. Participating in technical campaigns to drive Synopsys solution adoption through hands-on involvement. Acting as a customer advocate while interfacing with the product development team to influence product roadmap and future technologies. Contributing to technical articles in the Knowledge Base to provide self-help guidance for common customer issues. Rolling out new product methodologies by providing training and technical support to customers. The Impact You Will Have: Delivering comprehensive support and effective technical solutions to enhance customer satisfaction. Driving innovation by addressing design challenges and improving product performance based on customer feedback. Collaborating with R&D teams to advance future technologies and product features. Promoting Synopsys tools to grow market presence and adoption. Ensuring seamless EDA transitions to optimize customer outcomes. Strengthening Synopsys reputation as a leader in silicon design and verification.

Providing technical support and expertise to global customers using Synopsys Implementation products. Engaging in specific flagship projects and providing enabling solutions in all parts of the design implementation flow. Participating in technical campaigns to drive Synopsys solution adoption through hands-on involvement. Acting as a customer advocate while interfacing with the product development team to influence product roadmap and future technologies. Contributing to technical articles in the Knowledge Base to provide self-help guidance for common customer issues. Rolling out new product methodologies by providing training and technical support to customers. The Impact You Will Have: Delivering comprehensive support and effective technical solutions to enhance customer satisfaction. Driving innovation by addressing design challenges and improving product performance based on customer feedback. Collaborating with R&D teams to advance future technologies and product features. Promoting Synopsys tools to grow market presence and adoption. Ensuring seamless EDA transitions to optimize customer outcomes. Strengthening Synopsys reputation as a leader in silicon design and verification.

Managing a team of software engineers to develop and optimize test vectors for VLSI chip testing. Coordinating with multiple teams to ensure seamless integration and functionality of software solutions. Programming in C/C++ to develop high-quality software for detecting manufacturing defects in VLSI chips. Conducting rigorous testing to ensure the reliability and performance of software solutions. Learning from existing documentation and source code to integrate new ideas and improve algorithms. Engaging in continuous improvement of software quality and performance. The Impact You Will Have:Enhancing the reliability and performance of VLSI chips used in advanced technologies like AI and automated cars. Ensuring the highest quality of integrated circuits delivered to major design houses. Driving innovation in chip design and validation through optimized software solutions. Contributing to the success of Synopsys cutting-edge technology in the semiconductor industry. Improving the efficiency and effectiveness of software development processes. Fostering a collaborative and high-performing engineering team. What You will Need: Proficiency in programming, preferably in C/C++. Experience in managing and leading small teams of software engineers. Strong knowledge of data structures and algorithms. Good understanding of digital logic and VLSI concepts. In-depth understanding of timing analysis in VLSI.

Serving as the primary technical interface with customers, assisting them in evaluating, using, and applying TCAD tools. Providing technical support, troubleshooting, and resolving complex issues related to TCAD products. Managing new and existing customer relationships, ensuring high levels of customer satisfaction. Preparing and delivering technical training and presentations to customers and internal teams. Conducting beta testing, benchmarking, and onsite evaluations to support product development and customer needs. Collaborating with R&D to specify new features and drive continuous product improvement. The Impact You Will Have: Enhancing customer experience and satisfaction with Synopsys TCAD products. Driving the successful adoption and integration of TCAD tools in leading semiconductor companies. Contributing to the development and refinement of state-of-the-art TCAD tools. Strengthening Synopsys market position through exceptional technical support and customer engagement. Facilitating knowledge transfer and training to empower customers and internal teams. Playing a key role in the continuous innovation and advancement of semiconductor technology. What You ll Need: PhD in Electrical Engineering, Physics, or a related field. Strong background in semiconductor manufacturing technology and device physics. Proficiency in numerical methods and simulation tools. Excellent IT skills, particularly in Linux, Python, and TCL scripting. Minimum of three years of experience with TCAD simulation tools. Who You Are: A proactive and customer-oriented professional with excellent communication skills. Detail-oriented with strong problem-solving abilities. A collaborative team player who thrives in a dynamic environment. Adaptable and able to manage multiple priorities effectively. Passionate about technological innovation and continuous learning.

Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B. E/B. Tech with 2+ years or M. E/MTech inElectronics/Electricalof experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149. 1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We re doing work that matters. Help us solve what others can t.

Company Overview Group/Division Enabling the movement toward advanced chip design, KLAs Measurement, Analytics and Control group (MACH) is looking for the best and brightest research scientists, software engineers, application development engineers and senior product technology process engineers to join our team. The MACH teams mission is to collaborate with our customers to innovate technologies and solutions that detect and control highly complex process variations at their source rather than compensate for them at later stages of the manufacturing process. With over 40 years of semiconductor process control experience, chipmakers around the globe rely on KLA to ensure that their fabs ramp next-generation devices to volume production quickly and cost-effectively. Our MACH team develops leading-edge solutions for patterning process analytics and control technologies, thereby providing customers with critical insight at the feature level, field level and cross-wafer analysis. Our teams also develop advanced modeling simulation, data analytics and process control modeling technologies. As a member of the MACH team, you ll be joining the most sophisticated and successful process-control company in the semiconductor industry--working across functions to solve the most complex technical problems in the digital age. Job Description/Preferred Qualifications Required Qualifications: Designing and implementing physical and virtual server infrastructures In-depth knowledge of one or more flavors of Linux: RedHat, CentOS, Rocky, Ubuntu Experience in System-D, iSCSI, Multi-pathing, and Linux HA Experience creating Visio Diagrams to document deployments Experience Racking and Cabling in a Datacenter Environment Ability to code and develop Shell and Python scripts or experience using Ansible/Terraform Strong understanding of TCP/IP fundamentals and Knowledge of protocols, DNS, DHCP, HTTP, LDAP, SMTP. Experience with Storage Appliance Prefer Qualifications: Knowledge of Docker and Kubernetes deployments Experience with VMWare or KVM Virtualization Environments Knowledge of Network infrastructure technologies, such as firewalls, switches, and routers Knowledge of troubleshooting network and storage issues. Knowledge of cloud (AWS / Azure) IaaS, EC2, EKS, AKS, AVD etc Skills and Abilities: Team Orientation & Interpersonal - Highly motivated teammate with ability to develop and maintain collaborative relationships with all levels within and external to the organization. Organization & Time Management - Able to plan, schedule, organize, and follow up on tasks related to the job to achieve goals within or ahead of established time frames. Multi-task - Ability to expeditiously organize, coordinate, manage, prioritize, and perform multiple tasks simultaneously to swiftly assess a situation, determine a logical course of action, and apply the appropriate response. Adaptability to Change - Able to be flexible and supportive, and able to assimilate change positively and proactively in rapid growth environment. Minimum Qualifications Doctorate (Academic) Degree and 0 years related work experience; Masters Level Degree and related work experience of 3 years; Bachelors Level Degree and related work experience of 5 years

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelors degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for implementing and validation DFT/Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Implementation of various DFT/DFX features, Scan/MBIST Insertion & Validation, ATPG , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN Insertion / ATPG / MBIST / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Knowledge on various DFT/Test solutions Understanding of DFT Flows and Methodologies and Experience with Siemens/Synopsys/Cadence Tool set (Tessent/DC, Spyglass, Tmax, VCS/Genus, Modus, NCSim ) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product. We are seeking a seasoned SoC leads to work with a team to solve complex problems while optimizing performance, area, and power on leading-edge SoC systems. This team helps build new and innovative connectivity products tailored to world changing solutions for AI accelerators, Compute, IO, and Memory Chiplets. What Youll Do: You will manage the design / RTL team to achieve the project goals You will work with customer, provide technical support and provide collaterals agreed upon. You will work with team to achieve flow, methodology improvements to achieve high reuse. You will work with IP vendors to generate / get right configurations of the IP. You will manage teamwork allocation, schedule, risk mitigation and deliverables from design team. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for the SOC. Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with the cross-functional team of verification, DFT, Physical Design, emulation, and software teams to make design decisions and represent Design status throughout the development process. What youll have: Education: Bachelors or masters degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 15+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 15+years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

We are currently seeking Verification Engineer with strong verification fundamentals to work in Switch Silicon group. Youll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, youll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace. What youll be doing: Verify Switch designs architecture and micro-architecture using advanced methodologies. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level. Use sophisticated verification methodologies like e-specman, SV-UVM etc. What we need to see: BS (or equivalent experience) / MS with 4+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.). Perl/python scripting language experience desirable. Ways to stand out from the crowd: Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good social skills and ability desire to work as an excellent teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid

Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: Energetic, experienced, and organized, you are a writer who thrives in a vibrant environment and is passionate about cutting-edge technology You have a knack for turning complex technical information into clear, concise, and user-friendly documentation With a strong background in technical writing within the software or hardware industry, you bring a blend of creativity and precision to your work You are a team player who can also work independently, and you take pride in delivering high-quality content on time Your excellent communication and interpersonal skills enable you to collaborate effectively with engineers and other stakeholders You are always eager to learn and adapt to new technologies, ensuring that your documentation remains relevant and up-to-date If you care about doing a good job, about details, and about contributing to a dynamic team, Synopsys is the place for you, What Youll Be Doing: Planning, organizing, writing, and editing a variety of customer documentation, Collaborating with engineers to understand product functionalities and features, Creating user manuals, reference guides, and online help content in various formats, Ensuring documentation is accurate, clear, and comprehensive, Maintaining and updating existing documentation to reflect product updates, Utilizing authoring tools such as FrameMaker and Oxygen to produce high-quality content, The Impact You Will Have: Empower customers to effectively use and optimize Synopsys products, Enhance user experience through clear and accessible documentation, Support product adoption and customer satisfaction, Contribute to the success of product releases with timely and accurate documentation, Facilitate better communication and understanding between customers and the engineering team, Help maintain Synopsys' reputation as a leader in semiconductor IP solutions, What Youll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering disciplines Other technical disciplines considered, 3-5 years of technical writing experience in the software or hardware industry, Excellent problem-solving skills with strong logical reasoning, Proficiency with authoring tools such as FrameMaker and Oxygen, Excellent English writing and speaking skills, Who You Are: Excellent communication and interpersonal skills, Energetic and capable of learning new technologies as necessary, Team player with the ability to work independently, Detail-oriented and committed to delivering high-quality work, Proactive and able to take ownership of projects with minimal supervision, The Team Youll Be A Part Of: You will be part of a dynamic and experienced Technical Publications team that works closely with world-class engineers to create essential customer documentation Our team is committed to empowering customers worldwide with comprehensive and user-friendly content that enhances their experience with Synopsys products, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with a passion for GPU-accelerated systems and algorithm optimization With a strong background in computer science and extensive experience in GPU technologies like CUDA, OpenCL, or ROCm, you excel in designing and implementing high-performance solutions Your expertise in C++ and Python, along with your ability to troubleshoot and collaborate effectively, makes you an ideal fit for this role You are proactive, innovative, and always stay abreast of the latest trends in GPU technology Your ability to lead benchmarking and performance testing initiatives showcases your commitment to delivering optimal solutions for cutting-edge ILT software in the EDA industry, What Youll Be Doing: Optimize existing GPU implementations for ILT software, Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT, Collaborate with cross-functional teams to ensure seamless integration of GPU features, Lead benchmarking and performance testing initiatives, Stay current on GPU technology trends and design the latest advancements into the system, Work closely with customers and hardware vendors to deliver optimal solutions rapidly, The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations, Develop innovative GPU-accelerated algorithms that handle large-scale geometric data efficiently, Ensure seamless integration of GPU features into existing Mask Synthesis tools, Lead performance testing to ensure the highest standards of software quality, Drive technological advancements by integrating the latest GPU trends into our systems, Contribute to the rapid manufacturing of new chips by delivering optimal solutions swiftly, What Youll Need: S 6+ years of experience working with GPU-accelerated systems, Proficiency in CUDA, OpenCL, ROCm, or related technologies, Expertise in C++ and Python, Experience in distributed computing environments, Strong troubleshooting and collaboration skills, Who You Are: Innovative and proactive with a keen interest in the latest GPU technologies, Detail-oriented with strong problem-solving skills, Effective communicator who excels in collaborative environments, Dedicated to delivering high-performance solutions and continuous improvement, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a highly skilled and collaborative team focused on developing and optimizing GPU-accelerated algorithms for ILT software Our team works closely with other cross-functional teams, customers, and hardware vendors to ensure the seamless integration of GPU features and the delivery of optimal solutions We are committed to staying at the forefront of technological advancements and driving innovation in the EDA industry, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,