ASIC SOC RTL Design Lead (Micro-architecture)

Hi All,

Greetings' from Eximietas Design....!

ASIC SOC

Job Title:

Experience:

Location:

ASIC SOC RTL Design

Key Responsibilities:

• Define and develop

  microarchitecture specifications

  for complex SoC designs.
• Lead

  RTL design and implementation

  using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA).
• Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution.
• Perform

  design trade-off analysis

  to meet functional, performance, and power requirements.
• Develop and implement

  design methodologies

  to improve efficiency and quality.
• Mentor and guide junior engineers, fostering a culture of innovation and excellence.
• Participate in design reviews, provide technical leadership, and ensure adherence to project timelines.

Qualifications:

• 10+ years of hands-on experience

  in RTL design and microarchitecture development.
• Strong expertise in

  RTL design using Verilog/SystemVerilog

  and

  logic synthesis

  .
• Proficiency in

  microarchitecture design

  for complex SoCs, including

  pipelining, caching, and memory subsystems

  .
• Experience with

  low-power design techniques

  (e.g., clock gating, power gating, multi-Vt optimization).
• Familiarity with

  advanced process nodes

  and their specific challenges (e.g., finFET, multi-patterning).
• Strong scripting skills in

  Tcl, Python, or Perl

  for automation and flow development.
• Excellent problem-solving skills and attention to detail.
• Strong communication and leadership skills.

What We Offer:

• Opportunity to work on

  cutting-edge semiconductor designs

  and innovative technologies.
• Collaborative and inclusive work environment.
• Competitive compensation and benefits package.
• Professional growth and development opportunities.

maruthiprasad.e@eximietas.design