Application Specific Integrated Circuit Design Engineer

As an ASIC/SOC Front End Design Engineer, you will be responsible for setting up ASIC QA flows for RTL design quality checks. Your key responsibilities will include: - Understanding the design intricacies such as top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. - Executing tasks like Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP steps. - Developing clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. - Identifying and resolving flow errors, design errors, violations, and reviewing reports. - Debugging CDC, RDC issues, and implementing RTL fixes. - Collaborating with the DFX team for DFX controller integration, Scan insertion, MBIST insertion, and DFT DRC & MBIST checks. - Managing multiple PNR blocks, creating wrappers, and applying constraints and waivers. - Porting flows or designs to different technology libraries. - Generating RAMs using targeted memory compilers and integrating them with the RTL. - Performing functional verification simulations when required. Qualifications required for this role include: - B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience. - Proficiency in ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes. - Familiarity with modern SOC tools such as Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, and VCS simulation. - Experience in signoff of front-end quality checks & metrics for various project milestones. - Strong skills in TCL, Perl, and Python scripting. Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate,