Application Specific Integrated Circuit Design Engineer

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion, MBIST insertion, and DFT DRC & MBIST checks. The role also involves managing multiple PNR blocks, building wrappers, porting flows or designs to different technology libraries, generating RAMs based on targeted memory compilers, and integrating them with the RTL. Functional verification simulations will be run as necessary. The ideal candidate for this position should hold a B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience in ASIC design flow, particularly in sub-20nm technology nodes. Proficiency in modern SOC tools like Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, and VCS simulation is required. Experience in signoff of front end quality checks & metrics for various project milestones is essential. Additionally, familiarity with TCL, Perl, and Python scripting is preferred. This position is based in Hyderabad with an immediate start date. The desired candidate should have 3 to 5 years of experience in the field.,