Application Specific Integrated Circuit Design Engineer ACL Digital

3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

As an ASIC/SOC Front End Design Engineer, you will be responsible for setting up ASIC QA flows for RTL design quality checks. Your key responsibilities will include: - Understanding the design intricacies such as top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. - Executing tasks like Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP steps. - Developing clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. - Identifying and resolving flow errors, design errors, violations, and reviewing reports. - Debugging CDC, RDC issues, and implementing RTL fixes. - Collaborating with the DFX team for DFX c...

Posted 2 days ago

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Application Specific Integrated Circuit Design Engineer ACL Digital

3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion...

Posted 3 months ago

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