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1.0 - 6.0 years
0 Lacs
karnataka
On-site
Qualcomm India Private Limited is looking for an ASIC RTL Design Engineer with a minimum of 4 to 6 years of work experience. Your role will involve strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory for this position. You should have hands-on experience in handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. A solid understanding of multi-memory bus interfaces and functional safety BIST requirements will be a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is considered a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred. As a candidate, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience will also be considered. Qualcomm is an equal opportunity employer committed to providing an accessible process for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. It is expected that all employees at Qualcomm abide by applicable policies and procedures, including those related to security and protection of confidential information. This opportunity is only open to individuals seeking a job at Qualcomm. Staffing and recruiting agencies are not authorized to submit applications. For more information about this role, please reach out to Qualcomm Careers.,
Posted 2 weeks ago
7.0 - 12.0 years
35 - 60 Lacs
Bengaluru
Work from Office
Key Responsibilities: Develop and implement DFT architecture with a focus on MBIST for advanced SoCs. Integrate MBIST IPs, generate test insertion and verification infrastructure. Work on DFT planning, insertion, simulation, and pattern generation. Perform ATPG and MBIST pattern generation and debug failures from silicon bring-up. Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle. Support silicon bring-up and yield improvement activities post-silicon. Ensure high coverage and test quality in scan and MBIST. Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics or related field. Minimum 7 + years of hands-on experience in DFT with a strong focus on MBIST . Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent. Solid understanding of scan insertion, ATPG, boundary scan, and JTAG. Experience with memory test algorithms, repair analysis, and pattern generation. Familiarity with scripting languages (TCL, Perl, Python) for automation. Strong analytical and problem-solving skills with the ability to work independently please share or refer to below mail id - nishkalanka.nirmalakumar@tessolve.com
Posted 2 months ago
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