We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned SOC Engineering professional with a passion for pushing the boundaries of technology. With a Bachelor's degree in electronics engineering or computer science, and preferably a Master's, you bring at least 5 years of hands-on experience in physical verification and IR. Your proficiency in Verilog/VHDL, Unix, Perl, and TCL scripting makes you a valuable asset to any team. You have an in-depth understanding of microprocessor design, which sets you apart from the rest. Your strong written, verbal, and methodical skills enable you to communicate complex ideas effectively. You are driven by a desire to learn and grow, and you are excited by the opportunity to work on world-class microprocessors that allow customers to develop highly optimized and sophisticated embedded designs. What You’ll Be Doing: Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You’ll Need: Bachelor’s degree in electronics engineering or computer science; Master’s degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable. Who You Are: A detail-oriented professional with strong analytical skills. An excellent communicator with the ability to convey complex technical concepts effectively. A team player who thrives in a collaborative, international environment. A proactive learner who stays updated with the latest industry trends and technologies. A problem solver who enjoys tackling challenging technical issues. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on producing highly optimized hardware IP for the ARC family of configurable processors. Our team is dedicated to continuous improvement and innovation, and we work collaboratively with international colleagues to achieve our goals. You will have the opportunity to work on exciting projects, learn from industry experts, and contribute to the success of our world-class microprocessor IPs. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Bangalore,Karnataka,India Job ID 766880 About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. You'll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Driving Execution Be responsible for IP (Intellectual Property) development section, including design and verification at the subsystem, block, and/or sub-block levels. Act as an interface towards stakeholders and vendors. Ensure good collaboration with other teams both on-site and cross-site Team Recruiting and Development Recruit and develop team designers and verifiers Manage individual and team performance Develop a motivating, customer oriented and exciting work environment Broader Responsibilities Be an active contributor to the leadership teams of that global functional department that you collaborate with as well as the local IP development department Act as the chair and participate in steering groups inside organization or towards external suppliers Drive internal efficiency, cost effectiveness via new or alignment of existing ways of working, across all other design sections continuous improvements and automation Set goals, follow-up and strategically evolving section towards vison Required Qualifications: Bachelor’s degree in electrical or computer engineering Proven leadership experience in all the following areas IP development team management (at least 3 years) building a motivated, innovative, empowered team coaching and mentoring written and verbal communications and presentations ability to build on cultural diversity and collaborate across teams, organizations and sites working with external suppliers agile ways of working and project management 8+ years’ experience as an individual contributor designer or verifier Additional Requirements: Experience with Cadence and Synopsys design and verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

Bangalore,Karnataka,India Job ID 766876 About this Opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. You'll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of designer engineers, providing mentorship and guidance to ensure efficient and reusable design practices and IP. Collect and address, team status and metrics. Own and oversee the breakdown of requirements into actionable tasks for IPs and subsystems, ensuring alignment with project objectives. Review work done by the team, ensuring quality and adherence to design specifications. Take responsibility for deliverables, prioritizing work to ensuring successful completion in time. Continuously enhance and optimize design methodologies and processes, facilitating innovation and efficiency. Collaborate closely with IP System Architects and cross-functional teams to ensure requirements are effectively met. Work closely with the verification lead to support review and refinement of verification plans. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in ASIC design. Proven track record leading IP development and of successful cross-team and cross-site collaboration. Proficiency in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. Strong Experience with in low-power design, including specifying power intent using UPF or similar standards. Knowledge of Design for Test methodologies. Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a seasoned professional in analog IC design, you possess a deep understanding and hands-on experience with high-speed designs and FinFET technologies. You have a proven track record of working with Multi-Gbps NRZ & PAM4 SERDES IP and are familiar with various SerDes sub-circuits. Your expertise in transistor-level circuit design, combined with your strong analytical skills, equips you to tackle architectural bottlenecks and drive significant improvements in power, area, and performance. With excellent communication and documentation skills, you excel in presenting complex simulation data and collaborating with cross-functional teams. You are passionate about innovation and continuously seek to enhance design efficiency and quality through meticulous oversight of physical layouts and a keen awareness of design for reliability and signal integrity issues. What You’ll Be Doing: Review SerDes standards to develop novel transceiver architectures and sub-block specifications. Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets. Work across project and department teams to streamline design and verification strategies ensuring overall design quality, efficiency, and performance. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present and review simulation data from internal project teams; present results externally at industry panels or customer reviews. Document design features and test plans; consult on the overall electrical characterization of the SerDes IP product. Analyze customer silicon data for design enhancements and propose solutions for post-silicon design updates. The Impact You Will Have: Contribute to the development of cutting-edge Multi-Gbps NRZ & PAM4 SERDES IP, shaping the future of high-speed communication technology. Drive revolutionary improvements in power, area, and performance, enhancing the overall efficiency and effectiveness of our designs. Streamline design and verification strategies across teams, fostering a collaborative and innovative work environment. Ensure high-quality design and performance through meticulous oversight of physical layouts and awareness of design for reliability and signal integrity issues. Enhance customer satisfaction by analyzing silicon data and proposing effective design updates. Represent Synopsys at industry panels and customer reviews, showcasing our commitment to excellence and innovation. What You’ll Need: MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical Engineering, Computer Engineering, or a related field. Experience with FinFET technologies and a strong understanding of transistor-level circuit design and CMOS fundamentals. Extensive design experience with high-speed designs, including PAM4 SerDes architectures and various SerDes sub-circuits. Familiarity with tools for schematic entry, physical layout, design verification, and SPICE simulators. Exposure to scripting for post-processing of simulation results (e.g., TCL, PERL, MATLAB). Who You Are: You are a detail-oriented and innovative engineer with a passion for analog IC design. Your strong analytical skills and familiarity with high-speed designs enable you to tackle complex design challenges effectively. You excel in cross-functional teamwork and have excellent communication and documentation skills, making you a valuable contributor to both internal and external stakeholders. Your commitment to continuous improvement and reliability ensures that your designs meet the highest standards of quality and performance. The Team You’ll Be A Part Of: You will join a fast-growing analog and mixed-signal R&D team dedicated to developing high-speed analog integrated circuits in the latest FinFET and gate-all-around process nodes. Our team is composed of talented analog and digital designers from diverse backgrounds, working collaboratively to push the boundaries of innovation. Supported by a best-in-class environment with a full suite of IC design tools and custom in-house tools, our team is committed to delivering cutting-edge solutions that drive technological advancement. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for exploring new technologies and solving complex problems. With a minimum of 5+ years of related experience, you possess a comprehensive understanding of ASIC Physical Design and a working knowledge of multiple related areas. You are adept at using tools like DC, ICC2, StarRC, and PT-SI, and have a strong desire to continue learning and growing in your field. You thrive in both independent and collaborative work environments, frequently interacting with senior internal and external personnel to achieve project goals. Your excellent communication skills and ability to work as part of a team are crucial, as you will be engaging in daily technical interactions with both local and US counterparts. Experience in DDR power signoff and the ability to handle challenges such as timing closure above :2GHz, mixed signal macro IP integration, and building efficient clock trees with tight skew balancing are highly valued. What You’ll Be Doing: Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above :2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys' IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You’ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth. The Team You’ll Be A Part Of: You will be part of the SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team, focusing on the implementation and power signoff of world-class DDRs. This team is dedicated to pushing the boundaries of technology and delivering high-performance solutions that drive the future of computing. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Role Description Role Proficiency: Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Number of new projects handled Outputs Expected Quality of the deliverables: Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed Timely Delivery Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery Team Work Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available Innovation & Creativity Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills Good analytical reasoning and problem-solving skills with attention to details Able to deliver the tasks on-time per quality guidelines and GANTT in every instance. Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project Knowledge Examples Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill Additional Comments Job Description: Candidate must have good understanding of the System-Verilog, UVM and Test case development. Must have good debugging skills Required experience in Cadence Tool chain (Xcellium) Experience in AMBA protocol (AXI3/4, AHB, APB)Experience in usage of 3rd party VIP is plus Experience in PCIe protocol is plus Skills Design Verification,Xcellium,System Verilog,Test case development Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a talented, energetic, and experienced individual eager to join our Synopsys Cloud Operations Support team. You possess a strong foundation in Linux administration and Azure fundamentals, with a keen eye for detail and a dedication to maintaining comprehensive documentation and adhering to established processes. Your communication skills are exceptional, enabling you to convey technical concepts clearly to both technical and non-technical audiences. You excel in practical decision-making and agile goal delivery, thriving in a dynamic team environment where collaboration and problem-solving are key. Multi-tasking and effective prioritization come naturally to you, allowing you to manage R&D-related activities efficiently and communicate actions and results as needed. With a background in customer support, computer operations, or systems administration, you bring a wealth of experience to the table, particularly in UNIX system administration and network operations. What You’ll Be Doing: Designing, automating, and supporting Linux systems and services in a 24/7 production environment. Independently and collaboratively evaluating, recommending, and implementing technical solutions to meet business needs. Collaborating with other technical teams to solve problems and continually evolve the technology. Troubleshooting issues to identify root causes and help unblock the customer. Preparing and maintaining documentation of systems, standards, configurations, and procedures. Supporting day-to-day operations including installation, configuration, maintenance, and troubleshooting of the engineering secure computing environment. Responding to alerts, reporting issues, escalating problems as required, and resolving significant matters using independent judgment within established support practices. Ensuring compliance with Synopsys security policies to protect stakeholder information. The Impact You Will Have: Maintaining the high-performance Synopsys Cloud environment, ensuring smooth operations and compliance with security policies. Contributing to the overall reliability and scalability of our cloud infrastructure. Enhancing customer satisfaction by resolving technical issues promptly and effectively. Driving continuous improvements in our technology and processes through collaboration and innovation. Ensuring the security and integrity of our systems through vigilant monitoring and maintenance. Supporting Synopsys' mission to lead in chip design, verification, and IP integration by providing a robust and reliable cloud environment. What You’ll Need: Extensive knowledge of Linux operating systems and security patching. Experience with installing, monitoring, and administering Linux systems (Ubuntu and RHEL primarily). One or more Linux System Administrator Certifications. Experience with monitoring and logging tools. Programming/Scripting skills in Shell/Python. Basic Networking fundamentals including TCP/IP, DNS, subnetting, and routing. Knowledge of networking for virtual machines, particularly regarding security and performance. Knowledge of remote desktop software solutions such as VNC, Citrix Xen server, and VDI. Solid knowledge of infrastructure services like Kickstart, NFS, DNS, and DHCP. Knowledge in Azure resources like VM, Network, NSG, and Blob Storage is a plus. Who You Are: Ability to clearly communicate technical concepts to both technical and non-technical users. Proven ability to work in a dynamic team environment, collaboratively resolving problems spanning multiple disciplines. Enthusiastic and capable of learning on the job. The Team You’ll Be A Part Of: The team's purpose is to build, operate, and maintain a high-performance Synopsys Cloud environment. You will be part of a dynamic team that collaborates to solve complex problems and continually evolve our technology to meet business needs. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Description: We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a detail-oriented professional with flair for technical accounting, strong commitment to accuracy and compliance. You are a qualified accountant (CA/ CPA/ CMA) with 1-3 years of experience in in a high-growth software company or a large public accounting firm. You are familiar with US GAAP and have a sound understanding of revenue recognition principles under ASC 606. You thrive in a fast-paced environment and are a self-starter who can manage your time effectively. You possess excellent communication skills and can work collaboratively with multiple internal teams. Your proficiency in Excel and exceptional work ethic make you a valuable asset to the team. Your experience with SAP revenue accounting software RAR is a plus. What You’ll Be Doing: Assist with the review and approval of customer contracts, ensuring compliance with the company’s revenue recognition policy and accounting literature (ASC 606). Work with various internal teams including Order Management, Sales, Legal, Credit & Collections, and Professional Services to gather relevant information for decision-making. Assist in the preparation of revenue audit packages necessary for auditors to complete their quarterly and year-end audit selections. Conduct period-close activities in a timely manner. Maintain files and documentation thoroughly and accurately, in accordance with company policy and accepted accounting practices. Support team members, cross-functional teams, and the Manager with special projects including SSP study and Accounting memo’s as required. Maintain a customer service approach when interfacing with functional departments. The Impact You Will Have: Ensure accurate and compliant revenue recognition, critical for financial reporting. Improve the efficiency and effectiveness of revenue processes and audits. Contribute to the financial health and transparency of Synopsys through meticulous contract analysis and documentation. Facilitate smooth communication and decision-making across various internal departments. Enhance the overall customer service experience within the revenue accounting function. Support the company’s growth by managing high-volume periods with precision and expertise. What You Need: 1-3 years of experience with revenue recognition audit/ review exposure, either in a public accounting firm or a high-growth software company. University degree with a focus in business or economics; advanced degree or accounting certification (CA, CPA, CMA or equivalent) preferred. Excellent communication skills. Exceptional attention to detail, time-management, and customer service skills. Proficiency in Excel functions, including but not limited to VLOOKUP, SUMIF, Pivot tables, and IF statements. Exceptional work ethic. Show more Show less

Senior SoC Director / SoC Director Bangalore / Delhi / Pune / Chennai with some travel to Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in Interconnect Fabric Cache Coherency D2D C2C Oversee full chip design for complex SoCs. Develop and implement digital designs (RTL). Manage IP dependencies and track all front-end design tasks. Drive project milestones across design, verification, and physical implementation phases. Qualifications: At least 15-25 years of solid experience in SoC design. Proven ability to develop architecture and micro-architecture from specifications. Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C. Knowledge of memory controller designs and microprocessors is a plus. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Analog Design Engineer Skills & Experience Required: 5+ years of relevant experience. Has relevant knowledge and hands on experience of SerDes design at high data rates, up to 20Gbps. Study the assigned block, analyze the circuit carefully, and work on the hand analysis. Understand the required performance, the targeted specs and trade-off between different performance metrices. Write behavioral model of the circuit blocks for system-level simulations. Simulate and verifying designed schematics using Synopsys tools using circuit simulators. Debug to find out the root cause for any performance degradation. Being capable of solving all the faced issues. Working with layout team on layout optimization. Evaluate post layout performance using extraction tools (ICV and Calibre). Understand the interface with other blocks (if any) and work with other team members to optimize the interface. Coordinate and handling top-level simulations. Develop and executing characterization plans of the designed blocks, systems, and chips. Check the design reliability (EM/IR/Aging) using available tools. Do timing models using custom static timing analysis tools. Deliver the corresponding documentation as per the design process. Excellent knowledge of design/simulation tools such as Synopsys, Cadence and/or Mentor tools or any relevant tool. Good knowledge of any EM simulation tool. Good knowledge in behavioral modeling (Verilog, Verilog AMS). Very Good knowledge of custom timing static analysis tool (Synopsys NanoTime and SiliconSmart). Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaKolkata IndiaNoida S. KoreaSeoul Location - Bengaluru,Chennai,Kolkata,Noida

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What You Will Be Doing Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What We Need To See B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! JR1995153 Show more Show less

Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

The candidate will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing platform for our static verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, the candidate will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Person will work in platform team of static verification. Platform team provides support to various apps which are part of static verification. The hired candidate will provide features and support needed for successful deployment and ongoing business for apps of static verification. He might also work in developing GenAI application related to static platform. Technical competencies required for the role Strong hands-on experience in C/C++ based Object Oriented large and complex enterprise software development. Strong background in Design Patterns, Data Structure, Algorithms, and programming concepts. Well versed with Software Engineering and development processes. Experience with popular AI/ML frameworks (e.g., TensorFlow, PyTorch) is desirable. Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Ability to troubleshoot, debug, and support software applications. Good analysis and problem-solving skills. 4+ years of software development experience. Preferable skills Experience in EDA/AI/ML research and development Exposure to Tcl, Python, Shell scripting and/or Vim Exposure to developer tools such as gdb, Valgrind, Visual Studio and Eclipse. Exposure with source code control tool like Perforce, Clearmake, CVS or Git. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Graphics HW team in Bangalore is responsible for developing and delivering GPU solutions which are setting the power and performance benchmark in mobile computing industry. In this role of Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power. The Responsibilities Will Majorly Include: Understanding of GPU power and clock domains with power-up/down sequences Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging simulations and achieving all coverage goals Develop test plan to verify sequences and design components for Clock and power management modules. Explore innovative DV methodologies (formal and simulation ) to continuously push the quality and efficiency of test benches Successful candidate will be required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications Minimum 5 -8 years of design verification experience Senior positions to be offered to candidates with proven expertise in the relevant field Preferred Qualifications * 3+ years industry experience with below skillset : Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Basic understanding of low power design techniques Good understanding of design components such as clock gates, level shifters, isolation cells and state retention cells. Experience with Synopsys NLP (native Low Power) tool. Experience with scripting languages such as Perl, Python is a plus Education Requirements BE/BTech/ME/MTech/MS Electrical Engineering and/or Electronics, VLSI from reputed university preferably with distinction Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3067365 Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled Analog and Mixed-Signal Circuit Design Engineer with a passion for developing cutting-edge technology. With a strong foundation in circuit design fundamentals and a deep understanding of CMOS, device physics, and nanometer technologies, you excel in creating high-performance analog circuits. Your experience spans from designing transmitters and receivers to clocking circuits and serializers/deserializers. You are proficient in micro-architecting circuits from specifications, creating simulation environments, and debugging circuits. Your familiarity with high-speed designs, PAM4 serdes architectures, and automation/scripting languages further enhances your capabilities. You thrive in collaborative environments, working with global teams to deliver innovative solutions that drive technological advancements. What You’ll Be Doing: Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You’ll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies. The Team You’ll Be A Part Of: You will be part of a dedicated development team focused on High-Speed PHYSICAL Interface Development. This team comprises experienced professionals who collaborate locally and globally to deliver high-performance analog circuit designs. Together, you will push the boundaries of technology and contribute to the success of Synopsys' Silicon Design & Verification business. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You’ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys’ digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys’ capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You’ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a seasoned professional in RTL Design and Signoff, you bring a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems. You have a strong grasp of design and architecture, enabling you to develop precise timing constraints for synthesis and timing. Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of the curve. You collaborate effectively with peers to enhance methodology and execution efficiency. Your communication skills are excellent, facilitating smooth interactions with Synopsys customers, BU AEs, Sales teams, and other stakeholders. With a minimum of 8+ years of experience, you are well-versed in debugging, diagnosing violations, and setting up flows and methodologies for quick RTL Signoff tool deployment. Your technical expertise in LINT, CDC, RDC, and timing constraints development is unparalleled. You are a strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management. What You’ll Be Doing: Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Lead a team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems. Develop timing constraints for synthesis and timing while understanding the design/architecture. Collaborate with peers to improve methodology and enhance execution efficiency. Ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers. Work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions. Set up flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Ensure high-quality RTL Signoff and design, contributing to the success of Synopsys projects. Lead the team in delivering precise and efficient pre-silicon static verification activities. Enhance the overall execution efficiency of RTL Design and Signoff processes. Enable customers to achieve their goals through the deployment of Synopsys Products and methodologies. Develop and implement innovative solutions for RTL Quality Signoff in the semiconductor industry. Strengthen Synopsys’ reputation as a leader in chip design, verification, and IP integration. What You’ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 8+ years’ experience in RTL Design and Verification. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise in setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management. A leader who can guide and mentor a team of engineers. An excellent communicator who can effectively interact with customers and stakeholders. Adaptable and quick to ramp up on new tools and methodologies. Detail-oriented with a strong ability to diagnose and debug errors. The Team You’ll Be A Part Of: The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You’ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys’ digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys’ capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You’ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity. Show more Show less

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team. We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Show more Show less

About The Role Experience in Mixed-Signal layout design, holding bachelors degree in electrical/Electronic Engineering. To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experienceTSMC 7nm, 5nm, 10nm,28nm , 45nm,40nm EDA Tools Layout EditorCadence Virtuoso L, XL Physical verification DRC, LVS, Calibre Secondary Skills IO layout

Expert in floorplanning, P&R, CTS, STA, DRC/LVS. Proficient in Cadence/Synopsys tools, Perl/TCL scripting. Skilled in low-power techniques: voltage islands, power gating.

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR? Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications: BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us? Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Job Description: We are seeking a highly experienced and innovative Fellow to join our Physical Design (PD) Methodology team. The successful candidate will be responsible for driving advancements in PD methodologies, strategies, and tools to optimize the design and implementation of our semiconductor products. This role requires a deep understanding of physical design, EDA tools, and the ability to partner with cross-functional teams to achieve state-of-the-art design efficiency and performance. Key Responsibilities: Drive PD Methodology Innovations: Lead the development and implementation of cutting-edge physical design methodologies to enhance design efficiency, performance, and manufacturability. Strategic Planning: Develop and execute strategies that align with industry trends and company goals. Provide strategic direction for PD-related projects and initiatives. Methodology Development: Create and refine methodologies for physical design, including floorplanning, placement, routing, and timing closure. Ensure these methodologies are integrated into the design and development processes. End-to-End Design Optimization: Oversee the entire physical design process from initial concept to tape-out. Ensure design efficiency and performance are maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with RTL design teams, verification teams, and other engineering groups to integrate physical design methodologies across all levels of the system. Vendor Engagement: Collaborate with EDA tool vendors such as Synopsys and Cadence to ensure tools meet our design requirements. Drive joint development efforts and influence tool enhancements. Tool and Flow Automation: Lead efforts in the development and optimization of EDA tools for physical design. Work with tool vendors to ensure the tools meet our design requirements. Signoff Enablement: Ensure that all physical design methodologies and processes meet signoff criteria for manufacturability and performance. Technology and Library Enablement: Work with technology and library teams to enable new technologies and libraries in the physical design flow. PPA Optimization Guidance: Provide guidance on optimizing power, performance, and area (PPA) during the physical design process. Debug and Support: Lead efforts in debugging design issues and providing support to design teams to resolve complex physical design challenges. Industry Engagement: Stay abreast of the latest advancements in physical design within the semiconductor industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure physical design goals are met. Provide technical guidance and mentorship to team members. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in physical design techniques. Identify opportunities for patents and publications. Metrics: Define and track key performance indicators (KPIs) related to physical design efficiency and performance. Report on progress and impact to senior leadership. Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors #LI-SK5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education