906 Synopsys Jobs - Page 20

Analog Design, Sr Engineer-10559 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols Analog Circuit Design - CMOS circuit design and layout methodology & flow. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. What You’ll Be Doing: DDR/HBM Memory Interface I/O Circuit and layout design including GPIO and Special IO’s. Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications. What You’ll Need: Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design. Experience Required: 1 - 3 yrs Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements. The Team You’ll Be A Part Of: The team focuses on enabling our Interface IP customers to integrate the IP into their SoC and assist them through their design flows, debugging critical issues, and supporting silicon bring-up. This collaborative team works closely with customers to ensure the successful deployment of Synopsys' leading Interface IP products in various market segments. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Harman International is seeking highly driven and self-motivated RTL Design Engineers to join our cutting-edge semiconductor design team in Bangalore. This is a critical engineering role focused on synthesis, logic equivalence checking (LEC), and constraint development for high-performance digital IPs. You will be responsible for collaborating closely with architects, RTL developers, and other cross-functional teams to implement industry-standard design flows and methodologies. Responsibilities The ideal candidate is someone who has a strong understanding of physical design-aware synthesis, timing analysis, floor planning, and power optimization for advanced SoC and IP-level designs. Were looking for individuals who thrive in a fast-paced environment, are capable of taking full ownership of their deliverables, and can work independently with minimal Responsibilities : Collaborate with RTL designers and chip architects to implement synthesis, LEC (logic equivalence checks), and SDC (Synopsys Design Constraints) for NXPs digital IP designs. Own and drive physical-aware synthesis flows, including floorplanning and power/performance trade-off analysis for high-performance IPs. Perform timing and power analysis on the database (db), improve timing closure strategies, and provide actionable feedback to RTL and verification teams. Conduct timing signoff and static timing analysis (STA) using industry tools such as Primetime. Establish and maintain flow automation scripts for synthesis and LEC to support robust design delivery processes. Create and maintain design recipes to optimize timing, area, and power, ensuring delivery meets project milestones and design targets. Communicate effectively with cross-functional team members including verification, physical design, and program management to ensure smooth project execution. Take ownership as an individual contributor or lead engineer on specific IPs or subsystems, managing synthesis schedules and task breakdowns. Deliver weekly project status reports, capturing progress, challenges, and metrics around timing closure, synthesis QoR (Quality of Results), and tool flow efficiency. Desired Skills And Experience Experience : 3 to 12 years of relevant industry experience in RTL synthesis, LEC, and timing constraint development at the IP or SoC level. Strong understanding of synthesis flows, including setup from scratch and working with large-scale digital designs. Proficiency in using synthesis tools such as Synopsys Fusion Compiler, Design Compiler, or Cadence Genus. Hands-on experience with floorplanning, power optimization, and constraint development for advanced node designs (7nm/5nm/FinFET preferred). Solid understanding of timing analysis, multi-mode/multi-corner analysis, and power/timing closure methodologies. Practical knowledge of LEC tools like Conformal or Formality for equivalence checking. Familiarity with P&R (Place and Route) flow concepts and their influence on synthesis and timing constraints. Scripting expertise in TCL, Perl, and Python to automate design flows and reporting. Exposure to industry tools like Primetime, Innovus, and IC Compiler. Ability to work independently or as a team lead with minimal supervision and clear accountability for deliverables. Strong documentation and communication skills to maintain flow manuals and collaborate across geographically distributed teams. Preferred Qualifications Bachelor's or Masters degree in Electronics and Communication Engineering, VLSI Design, Computer Engineering, or a related field. Exposure to advanced SoC design and verification environments. Experience working in product companies or semiconductor IDMs will be considered a plus. (ref:hirist.tech) Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Bangalore,Karnataka,India Job ID 766878 About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly motivated and experienced ASIC Digital Design Architect with a passion for cutting-edge technology and innovation. You thrive in a collaborative environment and have a proven track record of delivering high-quality results in the field of digital design and verification. You possess deep expertise in interface protocols such as Ethernet, PCIe, and CXL, and have a strong understanding of both analog and digital mixed-signal design. Your ability to debug, diagnose, and support complex systems makes you an invaluable asset to any team. You are a problem solver who enjoys tackling challenging technical issues and delivering solutions that exceed expectations. You have a strong foundation in functional verification methodologies, including UVM and System Verilog, and are adept at scripting and automation using tools like Perl and Python. Your excellent communication skills enable you to effectively collaborate with cross-functional teams and support customers in achieving their goals. What You’ll Be Doing: Acting as a technical expert in one or more interface protocols (e.g., Ethernet, PCIe) to support development, verification, silicon validation, and customer support. Reviewing SERDES/PHY/Controller IP specifications to ensure compliance with relevant protocols. Developing and reviewing verification plans and environments, with a preference for UVM-based methodologies. Performing RTL, GLS, and co-simulations, ensuring functional and code coverage closure. Delivering high-quality RTL and simulation models to customers, along with verification components for integration into their environments. Supporting customers with IP bring-up in simulation environments and debugging silicon issues post-production. Demonstrating Testchip+FPGA system demos for customers and at industry conferences. The Impact You Will Have: Ensuring the successful development and verification of Synopsys’ multi-protocol 112G PHY IP, a critical component for high-end networking and computing applications. Driving innovation in the design and validation of industry-leading IP solutions that support multiple electrical standards, including PCIe 6.0, 400G/800G Ethernet, and more. Enhancing customer satisfaction by delivering high-quality IP and providing exceptional support during integration and silicon bring-up. Contributing to the advancement of cutting-edge technologies in the Era of Smart Everything, enabling smarter and more connected devices. Strengthening Synopsys’ position as a leader in chip design and verification through your technical expertise and innovative solutions. Representing Synopsys at industry conferences, showcasing the company’s capabilities and building strong relationships with customers and partners. What You’ll Need: A B.Tech/M.Tech degree with 15+ years of relevant experience in ASIC design and verification. Expertise in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Proficiency in functional verification methodologies, including VMM, OVM/UVM, and System Verilog. Experience with System Verilog Assertions, as well as code and functional coverage implementation and review. Fundamental knowledge of analog and digital mixed-signal design. Strong scripting and automation skills using Perl and Python. Excellent debugging and diagnostic skills to identify and resolve complex technical issues. Who You Are: A collaborative team player with strong communication and interpersonal skills. A detail-oriented professional with a commitment to delivering high-quality results. A proactive problem solver who thrives in a fast-paced, dynamic environment. A lifelong learner who stays up-to-date with the latest industry trends and technologies. A customer-focused individual who is dedicated to providing exceptional support and building lasting relationships. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team of engineers focused on developing and verifying Synopsys’ multi-protocol 112G PHY IP. This team leverages leading-edge design, analysis, simulation, and measurement techniques to deliver industry-leading solutions for high-end networking and computing applications. Together, you will drive innovation and shape the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less

Job Overview: Diacto is looking for a highly capable Data Architect with 5 to 9 years of experience to lead cloud data platform initiatives with a primary focus on Snowflake and Azure Data Hub. This individual will play a key role in defining the data architecture strategy, implementing robust data pipelines, and enabling enterprise-grade analytics solutions. This is an on-site role based in our Baner, Pune office. Qualifications: B.E./B.Tech in Computer Science, IT, or related discipline MCS/MCA or equivalent preferred Key Responsibilities: Design and implement enterprise-level data architecture with a strong focus on Snowflake and Azure Data Hub Define standards and best practices for data ingestion, transformation, and storage Collaborate with cross-functional teams to develop scalable, secure, and high-performance data pipelines Lead Snowflake environment setup, configuration, performance tuning, and optimization Integrate Azure Data Services with Snowflake to support diverse business use cases Implement governance, metadata management, and security policies Mentor junior developers and data engineers on cloud data technologies and best practices Experience and Skills Required: 5 to 9 years of overall experience in data architecture or data engineering roles Strong, hands-on expertise in Snowflake , including design, development, and performance tuning Solid experience with Azure Data Hub and Azure Data Services (Data Lake, Synapse, etc.) Understanding of cloud data integration techniques and ELT/ETL frameworks Familiarity with data orchestration tools such as DBT, Airflow , or Azure Data Factory Proven ability to handle structured, semi-structured, and unstructured data Strong analytical, problem-solving, and communication skills Nice to Have: Certifications in Snowflake and/or Microsoft Azure Experience with CI/CD tools like GitHub for code versioning and deployment Familiarity with real-time or near-real-time data ingestion Why Join Diacto Technologies? Work with a cutting-edge tech stack and cloud-native architectures Be part of a data-driven culture with opportunities for continuous learning Collaborate with industry experts and build transformative data solutions Competitive salary and benefits with a collaborative work environment in Baner, Pune How to Apply: Option 1 (Preferred) Copy and paste the following link on your browser and submit your application for automated interview process : - https://app.candidhr.ai/app/candidate/gAAAAABoRrcIhRQqJKDXiCEfrQG8Rtsk46Etg4-K8eiwqJ_GELL6ewSC9vl4BjaTwUAHzXZTE3nOtgaiQLCso_vWzieLkoV9Nw==/ Option 2 1. Please visit our website's career section at https://www.diacto.com/careers/ 2. Scroll down to the " Who are we looking for ?" section 3. Find the listing for " Data Architect (Snowflake) " and 4. Proceed with the virtual interview by clicking on " Apply Now ."

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Qualifications 8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. Education A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

The candidate will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. REQUIREMENTS: 4-9 years of experience in ASIC Physical Design Have good Hands on entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have hands-on experience in latest sub-micron technologies below 7nm Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Location :: Hyderabad & Bangalore *Adds on advantage atleast one or two projects has worked in AMD projects in his / her carier. Thanks, P Mohankrishna, Mohankrishna.p@Altcognitosystems.com Show more Show less

Company Description MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers located in Silicon Valley, USA, and India. Our expertise includes end-to-end silicon design, verification, systems, software, and device engineering, along with AI/ML solutions and test automation. MosChip® has an impressive track record with first-time right silicon of over 200 SoC tape-outs and has shipped millions of connectivity ICs. We provide comprehensive services including Digital IPs, Verification IPs, Mixed Signal IPs development, and Turnkey ASIC services. Role Description This is a full-time on-site role for a Senior Lead Physical Design Engineer located in Hyderabad. The Senior Lead Physical Design Engineer will be responsible for the complete physical design flow including, but not limited to, floorplanning, power planning, place and route, clock tree synthesis, and physical verification. The individual will also collaborate with cross-functional teams to ensure design specifications are met, timing closure is achieved, and design targets are aligned with company standards and customer expectations. Qualifications He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks’ closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs. Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: PD CAD Engineer Location:Hyderabad Work Type: Onsite Job Type: Full time Job Description: KEY RESPONSIBILITIES: Timing analysis and timing closure flow development and support , with focus on Synopsys Prime time, PrimePower, PrimeClosure Tools. Maintain and add enhancements to the AMD PD code flow Work closely with Design teams and EDA vendors to debug and fix issues in the PD flow and tools. Regressions to benchmark new Prime time tool versions PREFERRED EXPERIENCE: Experienced professional in PD, timing signoff and physical design Good understanding of advanced technologies in Prime time like Hyperscale and SMVA Good understanding of Physical Design implementation Good scripting skills in TCL, Perl or Python Work Experience 2-6 years TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Bangalore,Karnataka,India Job ID 766878 About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a proactive and detail-oriented individual with a passion for People Operations. With 0 - 2 years of experience in HR operations, you have a solid foundation in managing the employee lifecycle from pre-onboarding through offboarding. Your experience with HRIS systems, ServiceNow, particularly SuccessFactors or similar tools, equips you with the skills to handle complex employee data and processes. You hold a BA/BS degree and have honed your ability to manage multiple tasks and deadlines with exceptional organizational skills. Your strong stakeholder partnering skills enable you to collaborate effectively with various teams, ensuring the delivery of impactful HR solutions. You are familiar with Microsoft Office and project management tools, and your excellent written and spoken communication skills make you a reliable and clear communicator. Your resourceful problem-solving abilities allow you to troubleshoot issues independently and drive meaningful solutions. What You’ll Be Doing: Collaborate effectively with stakeholders to proactively determine and deliver relevant and impactful People (HR) operation solutions to business and system challenges. - Accurately perform employee lifecycle transactions/processes, including onboarding, offboarding, transfers/job status changes, timekeeping, time off and leave, extended workforce, and other responsibilities as assigned. - Recommend and draft employee lifecycle processes and procedures that enhance and optimize existing HR practices, ensuring they remain fit for purpose and benefit stakeholder teams. - Be a trusted resource for People (HR) systems, data, and process knowledge to interpret and analyze processes. - Drive People operation enhancements by supporting new module roll-out and optimization initiatives. - Manage requests, workflows, and develop a knowledge base and reporting metrics using ServiceNow. The Impact You Will Have: Streamline HR processes to improve efficiency and accuracy in employee lifecycle management. - Enhance stakeholder satisfaction by delivering timely and effective HR solutions. - Contribute to the optimization of HR practices, ensuring they are aligned with organizational goals. - Support the successful rollout and adoption of new HR modules and tools. - Provide valuable insights and data analysis to drive informed decision-making in HR operations. - Foster a collaborative and supportive HR environment, building trust with stakeholders and team members. What You’ll Need: 0 - 2 years of People (HR) operations related APAC work experience. - BA/BS degree. - Experience with HRIS administration, particularly SuccessFactors or similar tools. - Knowledge of managing requests, workflows, developing knowledgebase, and reporting metrics using ServiceNow. - Exceptional organizational skills and attention to detail. - Proficiency in Microsoft Office suite and familiarity with project management tools. - Excellent written and spoken communication skills. Who You Are: Detail-oriented and organized. - Resourceful problem-solver. - Effective communicator. - Collaborative team player. - Proactive and initiative-driven. The Team You’ll Be A Part Of: You will be part of a dynamic People Operations team focused on delivering exceptional HR services and solutions. Our team collaborates closely with various stakeholders to ensure smooth HR operations and continuous improvement of HR processes. We value innovation, teamwork, and a commitment to excellence in all our endeavors. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Senior/Lead ASIC Design Engineer Experience: 7+ Years IND, KA, Bangalore Silicon Systems Technology Group (SST) seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls. Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineers with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 8+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

This role is for one of Weekday's clients Min Experience: 8 years JobType: full-time Requirements About the Role: We are looking for a seasoned Logic Design Engineer with expertise in microarchitecture , RISC-V , VLSI , and VHDL , to lead the design and development of the L2 and Last Level Cache (LLC) for high-performance processor systems. This role is critical in delivering industry-leading CPU performance and efficiency by owning the complete lifecycle of cache architecture — from concept to pre-silicon signoff. As a technical leader in the team, you will be responsible for developing the microarchitecture of the cache subsystem, defining the RTL design, and collaborating across cross-functional teams including verification, DFT, physical design, and software/firmware groups to deliver world-class silicon. Key Responsibilities: Architect and design the L2 and LLC blocks for next-generation high-performance RISC-V processor systems. Translate system-level performance requirements — including capacity, latency, bandwidth, and RAS — into efficient, scalable cache architecture and microarchitecture solutions. Drive high-level feature definition and propose architectural enhancements in high-level design discussions. Develop detailed microarchitecture specifications and implement robust RTL designs in VHDL, ensuring performance, area, and power efficiency. Collaborate with the verification team to define verification plans, support testbench development, and debug RTL issues. Interface with DFT and physical design teams to integrate and optimize the cache subsystem for manufacturability and silicon readiness. Engage with firmware and software teams to support system bring-up and low-level programming interface development. Own pre-silicon signoff of the cache subsystem, meeting all functional, timing, and quality goals before tape-out. Continuously analyze performance metrics and identify areas of microarchitecture and logic improvements. Mentor junior engineers, contribute to design reviews, and participate in architecture working groups. Required Skills and Qualifications: 8+ years of experience in logic design and microarchitecture in high-performance CPU or SoC development. Deep expertise in microarchitecture and design of cache systems, memory hierarchies, or complex compute subsystems. Proven experience with RISC-V or RISC-based processor architectures and SoC integration. Proficient in RTL design using VHDL (Verilog/SystemVerilog is a plus). Solid knowledge of VLSI design principles, synthesis, STA, linting, and clock-domain crossing. Strong understanding of SoC design workflows and cache coherency, ECC/parity, and performance optimization techniques. Familiarity with performance modeling, cache hierarchy tradeoffs, and CPU-SoC system design. Excellent communication and collaboration skills to effectively interface with architecture, verification, physical design, and software teams. Preferred Qualifications: Experience with RISC-V core or cache subsystem development in commercial or open-source environments. Familiarity with scripting tools like Python, Perl, or Tcl for design automation and verification. Exposure to tools like Synopsys Design Compiler, VCS, or Cadence Genus and Innovus. Show more Show less

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the TD Advanced Modeling Group in Hyderabad you will work in a multi-functional team of engineers highly skilled in the modeling of materials, process, structure, and reactor, who are responsible for deploying modeling solutions towards advanced node development in TD and HVM. You will be responsible for developing predictive structure modeling simulations across multiple DRAM and NAND nodes. You will collaborate extensively with product design and process/integration teams for 3D structure model development, deployment, and providing solutions to be implemented on Silicon wafer. You will interact with process integration engineers and development teams to identify questions and issues hindering the node development milestones. Additionally, you will create programs, algorithms, and computational modeling solutions to extract concrete insights from modeling and data. You will interpret and convey these insights and findings from models and experiments to engineering teams and leaders. You are expected to work in a dynamic and fast-paced team environment developing and deploying models, communicating results to the team members, and collaborating with them on next steps. Qualifications: Master's or PhD degree in Applied Mechanics, Materials Science, Mechanical Engineering, or any related fields of engineering and physics . Possess 5+ years of strong Semiconductor process integration experience, driving structure specs, yield pareto issues for a product with hands-on (beginner level) experience in 3D semiconductor structure model building tools like Synopsys, Cadence, Mentor, and Silvaco . Understanding of analysis techniques like TEM/SEM/TDS and metrology techniques like Ellipsometry/WIS/Image based defect analysis. Experience with data analysis tools and machine learning frameworks (e.g., Python, MATLAB, TensorFlow). Experience with HPC on Linux environment Experience with computational geometry and mesh generation techniques is an added advantage. Excellent problem-solving skills and attention to detail. Ability to work independently and collaboratively in a fast-paced environment. Excellent written and verbal communication Experience with reports and presentations customized for users, managers and leaders Outstanding teamwork and experience with remote collaboration tools About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description: As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities and Tasks include, but not limited to: Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Qualifications: 8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. Education: A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Responsibilities: Assist in the development and validation of PDKs for various process nodes. Support the integration of technology files, DRC/LVS decks, and device models into EDA tools (e.g., Cadence, Synopsys). Write and maintain automation scripts (e.g., Python, TCL, Shell) to streamline PDK development processes. Collaborate with layout, design, and modeling teams to ensure PDK accuracy and usability. Troubleshoot and fix issues in PDK components related to DRC, LVS, parasitic extraction, and schematic symbols. Document PDK features, known issues, and development changes. Show more Show less

Job Description We are seeking a highly skilled C++ Python Developer with a strong background in software development, scripting, and EDA tool integration. This role focuses on creating, enhancing, and maintaining tools used in silicon design and verification environments. Required Skills & Experience 3+ years of hands-on experience in C++ software development. 2+ years of experience in Python scripting for automation or tool development. Strong grasp of object-oriented design, data structures, and algorithms. Hands-on experience with EDA tools (Synopsys, Cadence, Mentor Graphics) is a strong advantage. Proficient in Unix/Linux environments, including shell scripting. Solid understanding of software development lifecycle (SDLC) and design patterns. Strong debugging and profiling skills in both C++ and Python. Experience in unit testing and test automation frameworks (e.g., Google Test, PyTest). Knowledge of build systems (e.g., Make, CMake, SCons). Familiarity with code quality tools like linting, static analysis, and formatters. Excellent problem-solving, analytical, and communication skills. Preferred Qualifications Experience developing tools/scripts for chip design, EDA automation, or verification environments. Exposure to hardware description languages (HDLs) like Verilog or VHDL for tool integration. Understanding of semiconductor design flows (RTL to GDSII). Familiarity with version control systems (e.g., Git) and CI/CD pipelines. Knowledge of database integration (e.g., SQLite, PostgreSQL) for storing tool output or metrics. Experience with task automation frameworks like Airflow or Snakemake. Exposure to RESTful APIs for tool interoperability. Comfortable working in Agile/Scrum environments. Ability to manage and prioritize multiple tasks in a fast-paced, collaborative setting. Why Join Us? Join a technically strong and collaborative global team. Contribute to high-impact silicon and EDA automation projects. Flexible work arrangements and learning opportunities. (ref:hirist.tech) Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076513 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076510 Show more Show less