Microcircuits technology is looking for DFT Engineers to join our dynamic team and embark on a rewarding career journey. Research and draft blueprints, engineering plans, and graphics. Develop test prototypes. Identify solutions to improve production efficiency. Use design software to develop models and drawings of new products. Maintain existing engineering records and designs. Assess all engineering prototypes to determine issues or risks. Estimate cost limits and budgets for new designs. Supervise the manufacturing process of all designs. Coordinate with other engineers, management, and the creative department.

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

About The Role As part of the Design Technology Platform Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies, Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR); ESD Perc tools and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools. Direct reporting of Junior Engineers in the team will be involved and the candidate has to first level line manage the people and their deliverables day to day. Responsibilities includes:Define technical specification in the area of ASIC IR/EM and PERC ESD domain for Intel advance technology features to enable Intel-specific and industry standard EDA design tools. Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification. Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement. Build and qualify Process Pathfinding Kits and tools with quick turnaround time.Drive innovation and initiatives to enhance existing automation, tools and methodology. Identify and analyse problems, plans, tasks and solutions. Cultivate and reinforce appropriate group values, norms and behaviours. Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity.The candidate should also exhibit the following behavioural traits and/or skillsCreative, independent, and out of the box thinker with strong problem-solving skills and analytical ability. Experience in driving cross-functional and industry wide initiatives and taskforces.Attention to details, strong organization skills. Depth and Breadth being able to connect the dots and identify cross-discipline optimal solutions. Self-motivated, strong leadership skills being able to influence across internal and external ecosystem\Written and verbal communication skills to present complex issues with clarity to drive decisions. Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders. Ability to work in a dynamic and team-oriented environment. Qualifications BS in EE/CS with minimum 10 relevant industry experience OR MS in EE/CS with minimum 8 years relevant industry experience OR Ph.D. in EE/CS with minimum 5-year relevant industry experience in the following areas: Minimum 5+ year of people management skill. Extensive experience in running all aspects of the IR and EM flows for ASIC designs, must be expert in Ansys RHSC and Cadence Voltus and other In design RV flows and solutions. In depth understanding of EM and IR flows methodologies using Ansys RHSC and Cadence Voltus. Deep expertise in PERC ESD rule deck development in either Siemens Calibre or Cadence Pegasus or Synopsys ICV rule decks, new process node PDK enablement in PERC ESD space. This includes both Schematic front end design and in back end layout design side of implementation. Device level knowledge in ESD operational physics, expertise in modelling lower nm technology ESD complications and new challenging implementation and advancements.-Expertise and multiple years of exposure in implementation or solving Schematic checks, LDL - p2p, CD checks in layout side. Planning, execution and validation of Strategic new initiatives in area of PERC ESD implementation, PDK rule decks and new EDA engagements. Parasitic Extraction, Device Modelling and Simulation tools/flows. Expertise in building testcases, automation to run these EDA tools and interpretation of the results. Familiar with Reliability verification in lower nm nodes, EM/IR and ESD concepts, IO cell design and ESD execution. Familiarity with TVF, TCL and python automation in deep expertise extent. ICV python rule deck implementation expertise is preferred domain area. Excellent communication skills, able to clearly articulate the requirements to EDA vendors. Project management skills, to effectively and independently own the ASIC RV(EM/IR) tools certification and ESD perc flow methodologies. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

About The Role In this position, you will be responsible for managing and working on all aspects of STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to: Design and Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous and asynchronous paths, Clock domain crossing issues. Understanding and debugging extraction issues, deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting for partitions. Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff and quality checks. You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required. Qualifications EducationB.Tech. or M.Tech. in Electrical/Electronics Engineering with 10-14 years' of experience.PreferenceMaster's Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 10+ years of experience in STA.Key Skills: In-depth knowledge and hands-on experience with the overall silicon implementation flows and methodologies such as STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC. Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT/ETS). Skill in Synopsys tools (PT/DC) and exposure to ICC will be an added advantage. Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role The Graphics hardware IP team , within the CGAI Client Compute Group and AI, is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs GPUs, targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs ARC GPUs market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience. Minimum skills and Experience: Bachelors in Electrical/Computer Engineering or related field with 9+ years of academic or industry experience. Or a Masters in the same fields with 8+ Years of academic or industry experience. Your experience should be in the following: Experience across all the DFT features such as TAP/JTAG, SSN, Scan/ATPG or Array DFT (MBIST/PBIST), Silicon bring-up, DFT micro-architecture. SoC IP DFT design integration or verification. EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools, Synopsys tool. Silicon enabling debug or test pattern development experience Structural design flows, including timing, routing, placement or clocking analysis SOC architecture, RTL coding and post silicon debug. Experience in handling DFT timings constraints. Additionally: RTL insertion and integration will be a plus. Knowledge of UVM and OVM will be added advantage. Knowledge of system verilog is must. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

We are seeking an Analog Layout Engineer 3-8 for designing PMIC, converters, high-speed clocking circuits, and analog modules in FinFET, CMOS, and BiCMOS/BCD technologies Strong skills in layout, parasitic extraction, and verification tools required. Perks and benefits Competitive Salary Referral program Insurance

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated software developer with a strong foundation in C++ and Python programming and experience in data analysis. You are familiar with Machine Learning (ML) applied to data analysis and optimization problems. Your collaborative nature allows you to work seamlessly with cross-functional teams, including product application engineering (PAE) and front-end development teams, to deliver intuitive and effective solutions for our customers. You thrive in a dynamic, international environment and are eager to learn and apply new technologies to advance our TCAD products. Your ability to communicate complex technical concepts clearly and effectively makes you an invaluable asset to our team. What You’ll Be Doing: Design and implement Data Ingestion & Processing pipelines for our Sentaurus Calibration Workbench (SCW) – Format support, validation, DB with search/filters, AI/ML-driven analysis.Integrate core TCAD simulation engines with SCW – Optimize connectivity to reduce turnaround time (TAT), improve scalability, quality of results (QoR), and ease-of-use (EoU)Collaborate closely with the product application engineering (PAE) team to ensure functionality and quality requirements are met.Collaborate closely with the front-end team to ensure backend features are seamlessly integrated into the GUI for end-users. The Impact You Will Have: Drive advancements in TCAD calibration automation, leading to significant improvements in simulation efficiency and accuracy.Enhance the user experience by supporting integration of backend features into a user-friendly GUI, enabling seamless deployment of calibration workflows to customers.Support the creation of innovative solutions that address complex semiconductor design challenges, contributing to the success of our customers.Streamline the TCAD calibration process, reducing TAT and improving overall productivity for both internal teams and customers.Foster collaboration and knowledge sharing within the team, driving continuous improvement and innovation in SCW. What You’ll Need: MS or PhD in Computer Science, Software Engineering, Electrical Engineering, or equivalent.4+ years of hands-on experience in software development with solid programming skills in C++ and Python.Solid data analysis knowledge and skills.Familiarity and hands-on experience with ML applied to data analysis and optimization.Strong desire to learn and explore new technologies.English language working proficiency and communication skills allowing teamwork in an international environment.Willingness to work in a distributed international team. Who You Are: You are a proactive and innovative engineer with a passion for technology and a keen eye for detail. Your strong analytical skills enable you to solve complex problems efficiently, and your collaborative spirit ensures successful teamwork across diverse teams. You are adaptable and open to learning, always seeking to enhance your skills and contribute to the team's success. With excellent communication skills, you effectively convey technical concepts and foster a positive and productive work environment. The Team You’ll Be A Part Of: You will join the Sentaurus Calibration Workbench (SCW) team, a dynamic group of experts dedicated to developing and optimizing calibration workflows for TCAD simulation models. Our team collaborates closely with the product application engineering (PAE) team and front-end developers to deliver cutting-edge solutions that meet the evolving needs of our customers. We are committed to continuous innovation and excellence, driving advancements that shape the future of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

About The Role You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master's degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor's degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 12 years of experience, or MS/MTech degree with 10 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 10+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role About The Role : Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers.We are seeking a highly skilled and motivated STA (Static Timing Analysis) Engineer to join our team specializing in timing analysis for cutting-edge and complex SoC projects. This role offers a unique opportunity to work on high-level designs and collaborate with multidisciplinary teams in a dynamic and challenging environment. Your responsibilities may include but not be limited to: STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis and Timing Closure at Partition/Sub-system/FC level. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines. Familiar with Constraint Generation, development and clean up. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows. Work on Automation scripts with in STA tools for Methodology development. Familiar with digital design Implementation RTL to GDSII Synopsys/Cadence tools. Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics. Participate in and lead cross-functional meetings to drive project progress and resolve timing-related challenges. Act as a liaison between timing analysis and physical design teams, ensuring alignment and high-quality deliverables. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications Educational Qualifications: BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience in Electronics/VLSI/Computer Science or a related field. Preferred Qualification: At least 8+ years of experience in STA Timing Analysis using industry EDA tools. Experience in Python/Perl/TCL programming languages. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Role & responsibilities Perform fuzzing of network protocols on devices like routers, Wi-Fi routers, ONT/OLT, firewalls, and other network appliances. Research and develop fuzzing strategies to test network protocols, identify vulnerabilities, and improve security. Work with tools such as Synopsys Defensics, AFL, Peach Fuzzer, or similar for fuzzing network protocols. Collaborate with hardware and firmware teams to understand device functionality and how to target fuzzing effectively. Analyze crash reports and debug logs to identify root causes of vulnerabilities and provide detailed remediation steps. Prepare technical documentation and reports on the findings from fuzzing activities. Stay updated with the latest security trends, techniques, and tools in network protocol fuzzing. Preferred candidate profile Minimum 1 year of experience in fuzzing network protocols or security testing of network devices. Strong understanding of network protocols (e.g.TCP/IP, DHCP, DNS, HTTP, SIP, etc.). Experience with fuzzing tools (e.g., Synopsys, Defensics, AFL, Peach Fuzzer, Sulley, or custom fuzzers). Knowledge of network hardware, embedded systems, and operating systems. Familiarity with router, firewall, Wi-Fi router, ONT/OLT technologies, and associated protocols. Hands-on experience with debuggers, crash analysis, and memory corruption vulnerabilities. Solid understanding of network security concepts and vulnerability assessment techniques. Prior experience with security assessments and penetration testing of network appliances. Familiarity with scripting languages (e.g., Python, Bash) for automation of testing processes. Knowledge of reverse engineering and static/dynamic analysis of firmware. Certifications (Optional but Preferred) : OSCP, CEH, or other relevant security certifications.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10121 Date posted 03/21/2025 Job description (VC Spyglass Lint Technology on VC Platform) Responsible for designing, developing, troubleshooting the core VC-Static engine, which is integral part of Lint Design and develop Lint standard and customized Lint checks using VC Platform technologies for analysis, synthesis and simulations. Will be working closely with other teams both locally and globally Design and development of state of the art EDA tools involving development in one or more of the following areas-: developing new and innovative algorithms in the area of electronic design automation. Skills Required 4 to 10 years of Software development experience Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Fluent in C++ with work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Ability to develop new architecture Knowledge on GenAI is Value added Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success Quality focus – one who believes in quality and wants to make a difference Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9879 Date posted 03/21/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for cutting-edge technology and innovation. With 3-12 years of experience, you bring a wealth of knowledge in CMOS memory design and circuit implementation. Your expertise lies in developing non-volatile memories or SRAM. You are proficient in schematic entry, circuit simulation, layout planning, and design verification. You thrive in a collaborative environment, interfacing with CAD and Frontend engineers to drive memory compiler automation and EDA model generation. Your attention to detail ensures the highest quality in circuit and physical layout design. Self-motivated and self-directed, you demonstrate excellent analytical and problem-solving skills. You are adept at programming in C-Shell or Perl. Your strong command of English, both verbal and written, enables you to communicate effectively with team members and stakeholders. You are committed to continuous learning and professional growth, and you bring professionalism, critical thinking, and a focus on future goals to your work. Inclusion and diversity are important to you, and you contribute to a collaborative and inclusive work environment. What You’ll Be Doing: Develop CMOS embedded non-volatile memories such as MRAM and RRAM. Design architecture and circuit implementation, focusing on high speed, low power, and high-density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform design verification and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS non-volatile memory designs. Drive innovation in high speed, low power, and high density memory designs. Ensure the highest quality in circuit development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design(NVM or SRAM), circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Basic circuit know-how of Charge Pump, Voltage Regulator, Current Mirror, Reference voltage and current, Comparators preferred Programming capability in C-Shell or Perl Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development. The Team You’ll Be A Part Of: You will be a key member of our innovative R&D Engineering team, focused on developing cutting-edge CMOS embedded non-volatile memories (MRAM/RRAM). Our team thrives on collaboration and continuous improvement, working together to achieve technological advancements that shape the future. You will have the opportunity to lead and mentor junior engineers, contributing to a culture of learning and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

PREFERRED EXPERIENCE: • Minimum of 4-6 years' experience • Worked with EDA tools that enable RTL quality checks • Experience with analyzing the STA timing reports and identifying both the design and constraints related issues. • Ability to multitask, ramp up quickly on new flows/tools/ideas. • Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable Notice Period - 0 to 45 Days REQUIREMENTS: Attention to the detail Very good communication skills (both written and verbal) Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions) Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets Summarize the regression results periodically to track the progress. Able to debug the basic issues like SDC loading errors, check timing (no clock, unconstrained, no_clock, QoR violations)

Classic & Adaptive Autosar, co-simulation environments-VEOS & SILKIT,expertise tools-Synopsys,MATLAB/Simulink for vECU dev Dev level3/level4 vECUs for automotive app Design & implement s/w architectures adhering Classic & Adaptive Autosar standards Required Candidate profile Seeking a highly skilled Solutions Architect with extensive experience in automotive software development, particularly in the creation of level 3 or level 4 virtual Electronic Control Units (vECU).

As an FPGA & Board Design Engineer, you must develop new hardware designs, including system design, CPLD/ FPGA or processor design, and board-level analog/ digital circuit design for embedded systems/ boards. You have to develop detailed specifications based on requirements and implement Hardware designs in accordance with those defined requirements and/or specifications. Your duties include Schematic design generation and entry, netlist generation, and close interaction with the CAD team for layout review and feedback. Perform simulation activities including timing analysis, behavioural, and functional simulations. Develop test benches and other test tools as needed to complete the verification of FPGA designs. Carry out proto H/W bring-up with support from firmware engineers. REQUIREMENTS B.Tech. or M.Tech. EE with 2+ years of FPGA experience including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL and System Verilog. Proficiency in Synopsys Synplify, Xilinx Vivado, ISE Hands-on with FPGA debug methodologies, such as ChipScope. Proficient in Schematic capture tools like Orcad/Altium Hands-on experience with lab debug equipment such as oscilloscopes and logic analyzers. Strong scripting skills in Perl/Python. Experience in test bench design and implementation Knowledge of high-speed interfaces including PCIe, Ethernet, and DDR3/4. Knowledge of low-speed interfaces including SPI, IIC, and UART. Knowledge and experience designing with Altera and Xilinx FPGAs. Detail-oriented individual with good interpersonal skills and excellent written and verbal communications skills.

Hyderabad, Telangana, India Category: Information Technology Hire Type: Employee Job ID 10201 Date posted 03/20/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Business Analyst with over 10 years of experience in IT, including at least 7 years in software testing and quality-related roles. Your expertise in Tricentis Tosca automation, particularly with SAP, Salesforce, Oracle CPQ, APIs, and web applications, sets you apart. You have a deep technical knowledge and understanding of software testing best practices and are proficient in automating User Experience (UX) for web-based, API, and desktop applications, including Vision AI+. You excel in test data management, continuous integration/continuous deployment (CI/CD) pipelines, and integrating Tricentis Tosca with QTest. Your leadership experience in test automation, collaborative mindset, and excellent communication skills make you an invaluable asset to any team. You are customer-centric, always seeking to deliver unique solutions, and you thrive in agile environments. You are open to learning new skills and technologies to stay ahead in a dynamic industry. What You’ll Be Doing: Designing and developing Test Automation Frameworks, approach, and methodologies for large enterprise projects. Creating, maintaining, and executing end-to-end test cases, test scripts, and test data. Defining test automation strategy, best practices, project structure, and review processes. Performing test infrastructure setup, upgrades, and migrations, including Tricentis Tosca. Managing users, projects, and test portfolios using Tosca Server and Tosca Commander. Integrating Tricentis Tosca with third-party tools. Conducting regular reviews and maintenance of the test portfolio to ensure adherence to best practices. Defining upgrade and maintenance approaches and performing necessary upgrades and migrations. Collaborating effectively with global cross-functional teams and stakeholders. Mentoring and guiding team members on test automation best practices. The Impact You Will Have: Enhancing the quality and reliability of software products through robust automation frameworks. Streamlining testing processes, leading to faster time-to-market for our solutions. Ensuring seamless integration of Tricentis Tosca with other tools and platforms. Driving continuous improvement in testing methodologies and practices. Providing leadership and mentorship to junior team members, fostering a culture of excellence. Contributing to the overall success and innovation of Synopsys' technology offerings. What You’ll Need: Minimum 7 years of experience in Tricentis Tosca automation with SAP, Salesforce, Oracle CPQ, APIs, Web applications, etc. Expertise in automating User Experience (UX) for Web-based, API, and Desktop applications, including Vision AI+. Proficient in Test Data management using Tricentis Data Services (TDS) and Tricentis Test Case Design (TCD). Experience in DEX Configuration & Execution. Ability to set up Continuous Integration/Continuous Deployment (CI/CD) pipelines with Tricentis Tosca. Expertise in QTest integration with Tosca Certifications TRICENTIS Certified SAP Testing Specialist TRICENTIS Certified Tosca Architect TRICENTIS Certified Automation Engineer TRICENTIS Certified QTest Specialist TRICENTIS Certified Test Design Specialist Who You Are: As a professional with a sophisticated understanding of software testing and automation, you possess excellent written and verbal communication skills, enabling you to effectively engage with diverse audiences. You have a customer-centric approach, always striving to deliver unique and impactful solutions. Your collaborative mindset allows you to work seamlessly within global cross-functional teams, and your openness to learning new skills and technologies ensures you remain at the forefront of industry advancements. You are a proactive leader, advocating for test-driven development (TDD) practices and driving necessary changes to achieve optimal results. The Team You’ll Be A Part Of: You will join a dynamic team of forward-thinking professionals dedicated to advancing software testing and automation practices. The team focuses on integrating cutting-edge technologies and methodologies to enhance the quality and reliability of our software products. Collaboration, innovation, and continuous improvement are at the core of our team's values, and we strive to create an environment where every member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment. Education Requirements Required:Bachelor's, Electrical Engineering or equivalent experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. GPU Functional Verification Engineer In the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools "“ working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools "“ both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug GPU Functional DV ( Clock/Power) Verification Engineer In this role of Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power. The responsibilities will majorly include: Understanding of GPU power and clock domains with power-up/down sequences Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging simulations and achieving all coverage goals Develop test plan to verify sequences and design components for Clock and power management modules. Explore innovative DV methodologies (formal and simulation ) to continuously push the quality and efficiency of test benches Successful candidate will be required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills. Understanding of GPU power and clock domains with power-up/down sequences Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Basic understanding of low power design techniques Good understanding of design components such as clock gates, level shifters, isolation cells and state retention cells. Experience with Synopsys NLP (native Low Power) tool. Experience with scripting languages such as Perl, Python is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional About The Role : Minimum Qualifications Bachelor's degree in Science, Engineering or closely related field Experience with digital design and RTL development, Experience with front end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime Preferred Qualifications Knowledge and experience of graphics design and development Proficient in Perl, TCL and shell scripting Excellent interpersonal and team skills yet able to work independently and able to problem solve complex, unique and detailed issues Be Familiar with The latest EDA tools for synthesis, formal verification, timing analysis and physical design

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.