906 Synopsys Jobs - Page 19

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated individual with a passion for technological innovation and continuous improvement. You thrive in a fast-paced environment and are eager to contribute to cutting-edge projects. You possess a solid engineering understanding of the underlying concepts of IC design and have strong knowledge of the full design cycle from RTL to GDSII, including the development of timing constraints. Your expertise in the implementation flows and methodologies for deep sub-micron designs is unparalleled. You have experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution. You have a proven track record of contributing to project tape-outs and are proficient in timing closure and signal integrity. Your software and scripting skills (Perl, Tcl, Python) are top-notch, and you have knowledge of CAD automation methods. You are a team player who can interface with the larger product team to understand design constraints, deliverable formats, and customer requirements. With at least 3 years of physical design experience, you have hands-on experience with the design of complex ASSP and COT designs and are familiar with Synopsys tools, flows, and methodologies. What You’ll Be Doing: Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have: Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate with cross-functional teams to meet customer requirements What You’ll Need: Solid engineering understanding of IC design concepts Strong knowledge of the full design cycle from RTL to GDSII Expertise in implementation flows and methodologies for deep sub-micron designs Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution Proven experience with project tape-outs and timing closure Proficiency in software and scripting skills (Perl, Tcl, Python) Knowledge of Synopsys tools, flows, and methodologies Who You Are: You are a detail-oriented, innovative thinker with excellent problem-solving skills. You have a collaborative mindset and can work effectively in a team-oriented environment. Your strong communication skills enable you to convey complex technical concepts clearly. You are adaptable, continuously seeking to improve your skills and knowledge. You are dedicated to delivering high-quality results and are motivated by the opportunity to work on cutting-edge technology. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on physical design and implementation. Our team is dedicated to pushing the boundaries of technology and innovation. We work collaboratively to solve complex design challenges and deliver high-performance solutions. Joining our team means being part of a supportive environment where your contributions are valued, and your growth is encouraged. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for cutting-edge technology and innovation. With 3-12 years of experience, you bring a wealth of knowledge in CMOS memory design and circuit implementation. Your expertise lies in developing non-volatile memories or SRAM. You are proficient in schematic entry, circuit simulation, layout planning, and design verification. You thrive in a collaborative environment, interfacing with CAD and Frontend engineers to drive memory compiler automation and EDA model generation. Your attention to detail ensures the highest quality in circuit and physical layout design. Self-motivated and self-directed, you demonstrate excellent analytical and problem-solving skills. You are adept at programming in C-Shell or Perl. Your strong command of English, both verbal and written, enables you to communicate effectively with team members and stakeholders. You are committed to continuous learning and professional growth, and you bring professionalism, critical thinking, and a focus on future goals to your work. Inclusion and diversity are important to you, and you contribute to a collaborative and inclusive work environment. What You’ll Be Doing: Develop CMOS embedded non-volatile memories such as MRAM and RRAM. Design architecture and circuit implementation, focusing on high speed, low power, and high-density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform design verification and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS non-volatile memory designs. Drive innovation in high speed, low power, and high density memory designs. Ensure the highest quality in circuit development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design (NVM or SRAM), circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Basic circuit know-how of Charge Pump, Voltage Regulator, Current Mirror, Reference voltage and current, Comparators preferred Programming capability in C-Shell or Perl Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development. The Team You’ll Be A Part Of: You will be a key member of our innovative R&D Engineering team, focused on developing cutting-edge CMOS embedded non-volatile memories (MRAM/RRAM). Our team thrives on collaboration and continuous improvement, working together to achieve technological advancements that shape the future. You will have the opportunity to lead and mentor junior engineers, contributing to a culture of learning and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076511 Show more Show less

Radiant Semiconductors is a global player in Semiconductor Industry Founded in 2018, offering tailored semiconductor solutions to meet clients' needs, Headquarters in Bengaluru, Hyderabad and USA. Our services are RTL Design, ASIC Verification, Physical Design, DFT, Analog Layout, Analog Design and Physical Verification. Our dedicated and experienced team of engineers ensures delivery of high-quality results to accelerate clients' success. Trust in Radiant to illuminate your path to success. Why Radiant? 🌟 Competitive Salary & Benefits 📈 Career Growth Opportunities 🤝 Collaborative Work Environment 🎯 Cutting-Edge Projects We have Job Opportunity for Analog Layout Engineer Experience – 3 to 8 Yrs Location – Noida Availability – Immediate to 15 Days Job Description Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCS, DACS, voltage regulators) using TSMC/Samsung 7nm and below nodes. Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance. Required Skills: Strong experience in analog layout design at advanced nodes (TSMC/Samsung 7nm and below). Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar. Understanding of layout-dependent effects (LDE) and its impact on performance. Knowledge of parasitic extraction, simulation, and optimization. Familiarity with design for manufacturability (DFM) techniques. Knowledge on Basic SKILL/PERL. Show more Show less

Bengaluru, Karnataka, India Category: People Hire Type: Employee Job ID 10366 Date posted 06/18/2025 ; We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary leader with a deep understanding of Compensation and Benefits (C&B) strategies and their alignment with business goals. You thrive in dynamic environments and have a proven track record of designing and executing complex Total Rewards programs that drive employee engagement and organizational success. You are passionate about innovation and thought leadership in the HR space, and you excel at building systems and frameworks that deliver measurable outcomes. Your expertise spans across varied compensation plans, long-term grants, and benefits design. You are adept at setting the vision and strategy for C&B functions, ensuring alignment with talent acquisition and performance management systems. You are a strategic thinker who can link compensation frameworks to broader business strategies, and you are comfortable representing the organization in external HR forums as a speaker and thought leader. You are collaborative, detail-oriented, and results-driven, with exceptional communication skills that allow you to influence and inspire stakeholders at all levels. You are ready to lead a team and make a significant impact on Synopsys' Total Rewards strategy. What You’ll Be Doing: Setting the vision and strategy for the Compensation & Benefits (C&B) function, ensuring alignment with organizational goals. Leading the Total Rewards function, including deferred compensation plans, non-executive compensation plans, long-term grants, and benefits design. Designing and executing outcome-based health and wellness programs that enhance employee well-being. Directing complex C&B programs and projects, ensuring successful implementation and measurable results. Driving thought leadership and innovation in Total Rewards, positioning Synopsys as a leader in the HR space. Representing Synopsys in external C&B and HR forums as a speaker and key contributor. Collaborating with cross-functional teams to align compensation frameworks with talent acquisition and performance management systems. Setting up HR systems and processes that integrate business perspectives and deliver strategic value. The Impact You Will Have: Shape Synopsys' Total Rewards strategy to attract, retain, and motivate top talent. Enhance employee engagement and satisfaction through innovative compensation and benefits programs. Drive alignment between compensation frameworks and business strategies, ensuring organizational success. Position Synopsys as a thought leader in the HR space through external representation and contributions. Improve health and wellness outcomes for employees through strategic program design. Build robust HR systems and processes that support long-term organizational growth. Foster a culture of innovation and excellence within the Total Rewards function. Influence key stakeholders and drive strategic decision-making across the organization. What You’ll Need: Extensive experience in Compensation & Benefits, including deferred compensation plans, long-term grants, and benefits design. Proven ability to set vision and strategy for Total Rewards functions. Expertise in aligning compensation frameworks with talent acquisition and performance management systems. Strong project management skills, with experience directing complex C&B programs and initiatives. Thought leadership and innovation in the HR space, with a track record of external contributions. Who You Are: A strategic thinker with a deep understanding of business and HR alignment. A collaborative leader who excels at building relationships and influencing stakeholders. Detail-oriented and results-driven, with a focus on delivering measurable outcomes. An excellent communicator, both written and verbal, with the ability to inspire and influence. Passionate about innovation and continuous improvement in the HR space. The Team You’ll Be A Part Of: You will lead the Regional Compensation & Benefits team, reporting to the Global Compensation and Benefits leaders. This team is focused on driving Synopsys' Total Rewards strategy, ensuring alignment with business goals, and delivering innovative programs that enhance employee engagement and organizational success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Bangalore,Karnataka,India Job ID 768626 Grow with us About Us: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Key Responsibilities: Take part of the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 5+ years industry experience in verification using SystemVerilog and UVM. Additional experience will allow placement at higher job levels. Strong experience in / with: development of verification test plans and create directed/randomized test cases. formal verification. in implementing scoreboards, checkers, bus functional models in existing testbench environment. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are :The ideal candidate for the Project Engineering Management, Staff Engineer role is a seasoned Technical Project Manager with a strong focus on Product Security Compliance. You will leverage your exceptional project management skills to drive complex projects related to Open-source projects and Product Security. You will play a critical role in ensuring the security and integrity of our products while collaborating with cross-functional teams to drive initiatives that enhance our security posture .You will oversee the planning, execution, and delivery of complex security compliance projects. You will work closely with security engineers, product managers, business stakeholders, and IT teams to ensure that projects are delivered on time, within scope, and within budget. This role requires a strong understanding of Open Source, Product Security, and project management principles .In addition, you will coordinate cross-product dependencies, identify and escalate issues, manage risk and change from conception to delivery, and drive problem resolution through fact-based, conscious decision-making while promoting, implementing, and improving team, cross-functional, and cross-departmental business and engineering processes and practices . What You’ll Be Doin g:Manage security-focused projects, ensuring alignment with organizational goals and industry standard s.• Oversee security initiatives related to open-source projects, including assessing vulnerabilities, coordinating remediation efforts, and promoting best practices within the engineering team s.• Collaborate closely with stakeholders to define project objectives, scope, and deliverable s.• Develop and maintain comprehensive project plan s.• Drive effective communication and collaboration across cross-functional team s.• Monitor program progress and implement solutions to keep projects on trac k.• Drive continuous improvement initiatives by evaluating current processes and recommending enhancements to increase efficiency and security effectivenes s.• Proactively identify challenge areas and risks requiring executive engagemen t.• Identify issues and roadblocks, and escalate with the right level of details and priorit y.• Drive problem resolution through fact-based, conscious, and quality decision-makin g. The Impact You Will Ha ve:Ensure the security and integrity of Synopsys' products, particularly in open-source environmen ts.Lead the initiatives w.r.t product securi ty.Develop strategic project plans that align with organizational goals and industry standar ds.Facilitate cross-functional collaboration to enhance communication and project outcom es.Implement solutions to keep projects on track, ensuring timely delivery and high-quality resul ts.Promote best practices and continuous improvement initiatives within the engineering tea ms.Identify and mitigate risks, ensuring proactive management of potential challeng es.Provide valuable insights and recommendations based on data analytics, driving enhancements in product securi ty.Foster a culture of security awareness and compliance within the organizati on.Contribute to the overall success of Synopsys' security and data engineering initiativ es. What You’ll N eed:Project Management Experience: 2+ years of experience specifically in technical program management with overall experience of 8 to 12 ye ars.• Hands-on working knowledge in Python / Perl. Ability to do code reviews and take part in design discussi ons.• Product Security Knowledge: Strong understanding of product security principles, especially related to open-source proje cts.• Experience with cloud platforms such as AWS, Azure, or Google Cl oud.• Communication skills: Excellent verbal and written communication abilities for cross-functional collaborat ion.• Stakeholder Management: Ability to define project objectives and collaborate closely with stakehold ers.• Project Planning: Skills in developing and maintaining comprehensive project pl ans. Who You Are:A proactive and detail-oriented leader who can manage complex projects and drive them to successful comple tion.An excellent communicator who can effectively collaborate with cross-functional teams and stakehol ders.A strategic thinker with a strong understanding of product security and data engineering princi ples.A problem solver who can identify challenges and implement effective solut ions.A continuous learner who stays updated with the latest industry trends and best pract ices. The Team You’ll Be A Pa rt Of:This role helps Synopsys build products securely and be compliant with security standards. The EPMO team provides program management support to all the Synopsys Central Engineering programs and initiatives. The main focus of this role would be to ensure product security compliance and provide program management support to Data Engineering initiatives in Synopsys Central Engine ering. Show more Show less

Lead Physical Design Engineer | Hyderabad, India | Experience : 8+ Years Domain : Semiconductor – Physical Design About the Role: We are looking for a Lead Physical Design Engineer with deep expertise in working on mature/legacy nodes such as 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm . This role involves end-to-end ownership of physical design flow, from floorplanning to GDSII, with a strong emphasis on timing closure, IR/EM analysis, and physical verification . The ideal candidate should be technically hands-on and able to lead block-level or chip-level efforts with minimal supervision. Key Responsibilities: End-to-end execution of RTL to GDSII physical design for block- or full-chip Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff Manage timing closure , IR drop, EM, and congestion challenges effectively Handle physical verification (LVS, DRC, ERC, antenna checks) using standard sign-off tools Work closely with RTL, STA, DFT, and package integration teams Mentor junior team members and support physical design reviews and planning Required Skills: Proven experience on older technology nodes (e.g., 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm ) Hands-on with tools like Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC Expertise in timing constraints, physical ECOs , and sign-off methodologies Strong understanding of low power design, DFM, and hierarchical flows Ability to lead technically and communicate effectively across teams Educational Qualification: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI Design, or related disciplines Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com Show more Show less

🎯 We’re Hiring | Join Our Engineering Dream Team – India 🚀 Looking to shape the future of automotive, industrial, and semiconductor innovation? We're growing and hiring across multiple technical domains! Explore high-impact roles with global collaboration opportunities. 🌍 🔋 AMS Design Lead | Hyderabad • Lead next-gen automotive-grade PMIC design • Own Switcher IPs (DC-DC Converters) for global programs • 9+ yrs in analog design – references, amplifiers, loop compensation • Mentor teams & collaborate across international centers • Drive power-efficient & precision-focused innovations ✅ AMS Verification Lead | Hyderabad • 9+ yrs in Verilog-AMS, WREAL, UVM , AMS simulation flows • Build verification environments from scratch • Own sign-off strategies & mentor verification engineers • Expertise in co-simulation & mixed-signal modeling ⚙️ Embedded Software Applications Engineer | Pune • 5+ yrs hands-on embedded SW experience • Motor control expertise – FOC, Sensorless , C/C++, Cortex-M • Experience with full SW lifecycle (ASPICE L2) , debugging, protocols (SPI, I2C, UART) • Work with tools like IAR, GitLab, Oscilloscopes • Collaborate with global teams & travel opportunities 🛠️ Embedded Software Engineer – V&V | Hyderabad • 5+ yrs in Embedded SW V&V – VectorCAST, ASPICE/V-Model • C programming, MCU-based systems (ARM/STM/PIC), UART, CAN, SPI, I2C • Firmware integration, board bring-up & debugging • Familiar with Git, Keil, IAR • Bonus: C++, shell scripting, hardware interface 💾 Senior Physical Design Expert & Lead | Hyderabad • Hands-on Netlist2GDSII flow on advanced nodes (16nm & below) • Floor planning, power grid, CTS, STA , and physical verification • Tools: Cadence Innovus, Synopsys ICC2 • Strong in SoC integration & Tcl/Tk/Perl scripting • Proven leadership in physical design projects 🧪 Senior PSV Engineer & Lead – Hyderabad/Noida • Post Silicon Validation of Analog Mixed Signal IPs/SoCs • Strong analog/digital fundamentals • Experience with tools: Oscilloscope, NI-PXI, Spectrum Analyzer • Python & LabVIEW scripting for automation • Exposure to current sensor validation is a plus Interested? Apply or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

About the job Responsibilities Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic EDA team. Enable EDA flows and ensure tools are qualified on cutting edge IPs before rolling them to the wider community. Develops, maintains, debugs and tests SOC Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) to Back-End (GDS) flows seamlessly Take ownership, lead project and deliver results while guiding other engineers Verify CAD flows are generating correct results (flow signoff) and setup tool regressions Work closely with Engg IT and Database Mgmt teams to setup flows which work well with the Engineering Compute Infra in MaxLinear Datacenters Drive consensus across business units on tool & design methodology Work closely with technology and design teams to resolve signoff criteria Support design engineers on the flow setup and resolve their queries Qualifications MS/BS in Electrical/Computer Engineering with demonstrated experience in CAD or EDA tools flows architecture, development and support Demonstrated experience with various EDA software, flows and architectures & driving EDA vendors to improve tools to implement new functionality to solve problems or to optimize existing methods Must have worked on Digital flows/methodologies development in the domain of PD or DV. Should have proficient skills with one of PD related tools Genus/ Innovus /Tempus/ Calibre /FC/PT/DC. ( Or ) Should have proficient skills with one of DV related tools Xcelium /Questa/VCS/ vManager or equivalent. Must have strong scripting abilities in Python and/or Perl, tcl ; Must have UNIX knowledge and experience with data-management software Must have experience in taking ownership, leading projects along with guiding other engineers and producing results Ability to document design methodologies & provide training on tools and workflows to design teams Experience with Front-end Digital Design and/or PD and/or Digital Verification methodologies with a focus on digital and mixed-signal solutions Experience in defining and developing PD flow methodologies using Cadence/Synopsys/Siemens tools Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment Show more Show less

Hi All, Greetings from Eximietas Design...! We are hiring Senior Analog Layout Design Engineers/Leads. Experience: 4-12 years. Location: Hyderabad Job Description: ❖ Must understand techniques for managing IR drop, Electromigration, self-heating, RC delay and parasitic capacitance optimization. ❖ Understanding layout effects on the circuit such as speed and area. ❖ Ability to understand design constraints and implement high-quality layouts. ❖ Good communication skills and able to work with cross-functional teams. ❖ High level proficiency in C ADENCE/SYNOPSYS layout tools flow. ❖ Hands on experience on lower FINFET technology nodes. ❖ Scripting skills in PERL/SKILL are a plus. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design Show more Show less

Hi All, Greetings from Eximietas Design...! About the Job Function: ❖ Must have solid understanding of analog & mixed signal design fundamentals. ❖ Bandgap references and voltage monitors ❖ Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE and FFE ❖ Working Experience in Die to Die interconnect high speed IO designs, HBM, DDR and UCIe protocols ❖ Hands on experience on lower FINFET technology nodes ❖ Basic analog layout knowledge especially with FINFET technology ❖ Expertise in following tools and standards: ❖ Cadence and Synopsys mixed signal design tool flow ❖ The Candidate should have atleast 3 years of experience in Analog circuit design and be able to work independently. Location: Visakhapatnam, Bangalore & Ahmedabad Interested Engineers, please share your updated resume with maruthiprasad.e@eximietas.design Show more Show less

Responsibilities: Assist in the development and validation of PDKs for various process nodes. Support the integration of technology files, DRC/LVS decks, and device models into EDA tools (e.g., Cadence, Synopsys). Write and maintain automation scripts (e.g., Python, TCL, Shell) to streamline PDK development processes. Collaborate with layout, design, and modeling teams to ensure PDK accuracy and usability. Troubleshoot and fix issues in PDK components related to DRC, LVS, parasitic extraction, and schematic symbols. Document PDK features, known issues, and development changes. Show more Show less

Position: DFT Engineer (ASIC) Experience: 2 to 8 years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies . Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design. With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development. You possess a deep understanding of design concepts, ASIC flows, and stakeholder management. Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints. You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables. Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You’ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys’ reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You’ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years’ experience in SoC RTL Design. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive leader with excellent managerial skills. A team player who can mentor and guide engineers. An effective communicator who can interact with customers and stakeholders. A problem-solver with a keen eye for detail. An innovator who continuously seeks to improve processes. The Team You’ll Be A Part Of: As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Design Verification Engineer (3-7 years’ experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 3-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions Show more Show less

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal IP/RTL Design Engineer for Ethernet Switch Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Design Verification Manager Hyderabad www.Sevyamultimedia.com About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7-12 years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description Physical Deisgn Lea Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure. ͏ Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities ͏ 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for ‘will’ based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation ͏ Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) ͏ Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking a highly skilled Senior DevOps Engineer who is proactive and knowledgeable with a passion for cutting-edge technologies for the central software engineering organization at Synopsys. As an ideal candidate, you are experienced in driving engineering efforts related to Continuous Integration and Delivery (CI/CD), automated testing, and deployment across all phases of the Software Development Life Cycle. You are adept at implementing frameworks and best practices for deploying automation via pipelines into various environments including on-premises, cloud (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Your expertise lies in building platforms and frameworks that enable consistent, verifiable, and automated management of applications and infrastructure. You thrive in an Agile framework, identifying, creating, designing, and integrating processes for repeatable, automated software delivery. You are an advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. Your strong communication skills enable you to effectively design cross-functional deployments and triage efforts, and you possess excellent analytical and problem-solving abilities. Additionally, you are skilled in mentoring and providing oversight to other DevOps team members, guiding them in implementing recommended solutions for process automation and best practices. What You’ll Be Doing: Driving engineering efforts related to Continuous Integration and Delivery (CI/CD) and automated testing and deployment across all phases of the Software Development Life Cycle. Implementing frameworks and best practices for deploying automation via pipelines into on-premises, cloud environments (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Building platforms and frameworks to create consistent, verifiable, and automatic management of applications and infrastructure in both on-premises and cloud infrastructure. Defining the development pipeline to ensure that software development flows match operational testing and deployment goals. Working within the Agile framework to identify, create, design, and integrate processes for repeatable, automated software delivery. Identifying and initiating the development of metrics and dashboards to monitor the adoption and maturity of DevOps practices. Advocating for innovation and automation, continuously seeking ways to improve CI/CD processes. Reviewing technical operations and providing mentoring and oversight to other DevOps team members in implementing recommended solutions for process automation and best practices. The Impact You Will Have: Enhancing the efficiency and effectiveness of our CI/CD pipelines to ensure high-quality software delivery. Enabling consistent and automated management of applications and infrastructure, improving reliability and scalability. Streamlining the software development lifecycle, ensuring alignment with operational testing and deployment goals. Driving the adoption and maturity of DevOps practices through the development of metrics and dashboards. Fostering a culture of innovation and automation within the engineering team. Mentoring and guiding other DevOps team members, enhancing their skills and knowledge. What You’ll Need: Bachelor's or Master's degree in Engineering streams such as Computer Science, EEE, ECE, IT, or equivalent. At least 5 years of overall software development/deployment/infra experience. Cloud and other architect-level industry certifications (AWS, GCP, Azure, Security, etc.). 3-5 years of DevOps experience in modern tech stack to support products in the cloud. 2+ years of scripting/automation experience with Bash, Python, Perl, and/or other scripting languages. Strong CI/CD experience with code build, source control, testing, continuous integration, and delivery using standard DevOps CI/CD tools (Jenkins, Git). 3+ years of experience with containerization, source control (Docker/Docker Hub/Helm), and container orchestration (Kubernetes, Docker Swarm). Familiarity with programming languages (C/C++/Java). Familiarity with build tools (Make, CMake, Maven, Gradle) and dependency management (Conan). Experience developing Ansible Playbooks/Jenkins automation for infrastructure automation. Proficiency in multiple DevOps-related tools and technologies (JIRA, Confluence, GitHub/Azure, Jenkins, Ansible, Prometheus, Grafana, ELK). Who You Are: A proactive and knowledgeable engineer with a passion for cutting-edge technologies. An advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. A strong communicator, able to effectively design cross-functional deployments and triage efforts. An excellent problem solver with strong analytical skills. A mentor and guide, capable of providing oversight and guidance to other DevOps team members. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative central software engineering organization at Synopsys. The team is focused on driving engineering efforts and automating processes to deliver high-quality EDA products. We work collaboratively within an Agile framework, continuously seeking ways to improve and innovate in the field of DevOps. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less