Role Description Additional Comments:Physical Design Engineer Experience- 4 to 10 years Engineers is expected to be very good in Basic Fundamentals of C-MOS technology Expected to have a very good understanding of the PD Flow for flat and hierarchal designs Able to handle RTL/Netlist to GDSII independently at block level/SS/SoC and should have done multiple tape outs with low power implementation (Experience on floor planning, Partitioning, integration at Subsystem/Chip will be add advantage) Should have hands-on experience of working on Lower technology nodes like 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm Exposure in DMSA flow for ECO generation and implementation. Good knowledge of VLSI process and scripting in TCL, perl . Skills Physical design,PNR,PD Flow Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Analog Design Engineer with a strong passion for innovation and technology. With a solid background in analog design fundamentals and device physics, you excel at developing high-speed IO designs in advanced technologies. Your expertise in memory interface PHY IPs (DDR/HBM/UCIe) and your familiarity with JEDEC requirements position you as a valuable asset in our team. You are adept at collaborating with cross-functional teams, driving innovation, and ensuring the delivery of high-quality products. Your excellent written, verbal communication, and interpersonal skills enable you to effectively convey complex technical concepts and work seamlessly with colleagues across the globe. You thrive in a dynamic environment where you can leverage your skills to make a significant impact on the development of next-generation technologies. What You’ll Be Doing: Leading the development of next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe). Driving innovation towards high-speed IO designs for memory interface PHY IP in CMOS/FinFET/GAA. Collaborating with cross-functional teams across the globe to ensure seamless project execution. Ensuring compliance with JEDEC requirements for memory interfaces and standards. Implementing and validating ESD and reliability concepts in design processes. Focusing on signal integrity and power integrity to enhance product performance. The Impact You Will Have: Accelerating the development and integration of high-speed memory interface PHY IPs. Enhancing the performance and reliability of our silicon IP portfolio. Driving innovation in high-speed IO designs, setting new industry benchmarks. Facilitating cross-functional collaboration to achieve project milestones efficiently. Contributing to the successful launch of differentiated products in the market. Ensuring that our products meet the highest quality standards and customer expectations. What You’ll Need: BTech/MTech in Electrical Engineering or a related field. 8-15 years of experience in analog design and high-speed IO designs in advanced technologies. Proficiency in analog design fundamentals and device physics. Expertise in high-speed IO designs for memory interface PHY IPs (DDR/HBM/UCIe). Knowledge of JEDEC requirements for memory interfaces and standards. Understanding of ESD and reliability concepts. Familiarity with signal integrity and power integrity. Excellent written, verbal communication, and interpersonal skills. Who You Are: A proactive and innovative problem solver. A collaborative team player with exceptional communication skills. Detail-oriented and committed to delivering high-quality results. Able to work independently and manage multiple projects simultaneously. Adaptable to fast-paced and dynamic work environments. The Team You’ll Be A Part Of: You will be part of a highly skilled and collaborative team of engineers focused on developing cutting-edge memory interface PHY IPs. Our team is dedicated to pushing the boundaries of technology and delivering innovative solutions that meet the evolving needs of our customers. We work closely with cross-functional teams across the globe, ensuring that our products are of the highest quality and performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. You Are: You are a highly skilled and passionate engineer with a talent for tackling complex problems and a strong desire to advance cutting-edge technology. With over five years of experience in Physical Implementation RTL-GDS, you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. You are proficient in scripting languages like Tcl, Unix, and Perl, and possess an in-depth knowledge of Synopsys implementation tools. Your strong communication abilities enable you to engage effectively with both customers and internal teams, ensuring precise and attentive fulfillment of their needs. Driven, self-starting, and highly collaborative, you excel in environments where you can advocate for customers and represent the product. Additionally, your ability to translate technical insights into actionable requirements for R&D teams plays a crucial role in driving innovation and strengthening Synopsys solution capabilities. What You’ll Be Doing: Providing technical support and expertise to global customers using Synopsys Implementation products. Engaging in specific flagship projects and providing enabling solutions in all parts of the design implementation flow. Participating in technical campaigns to drive Synopsys solution adoption through hands-on involvement. Acting as a customer advocate while interfacing with the product development team to influence product roadmap and future technologies. Contributing to technical articles in the Knowledge Base to provide self-help guidance for common customer issues. Rolling out new product methodologies by providing training and technical support to customers. The Impact You Will Have: Delivering comprehensive support and effective technical solutions to enhance customer satisfaction. Driving innovation by addressing design challenges and improving product performance based on customer feedback. Collaborating with R&D teams to advance future technologies and product features. Promoting Synopsys tools to grow market presence and adoption. Ensuring seamless EDA transitions to optimize customer outcomes. Strengthening Synopsys' reputation as a leader in silicon design and verification. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. Expertise in Implementation Methodologies and Synopsys Tool Fusion Compiler. Knowledge of STA, Low Power Flows, Design Planning, and scripting languages like TCL/Python. Thorough understanding of RTL to GDS flows and methodologies. Excellent verbal and written communication skills. Experience in customer-facing roles is a plus. Deep domain knowledge in Synthesis, Place & Route, and timing analysis, with multiple chip tape-outs at 7nm or lower nodes. Who You Are: An effective communicator with strong interpersonal skills. A proactive self-starter who takes initiative and drives projects to completion. A collaborative team player who values teamwork and collective success. Detail-oriented and committed to delivering high-quality solutions. Adaptable and eager to learn new technologies and methodologies. The Team You’ll Be A Part Of: You will be part of a dedicated team of application engineers focused on providing top-notch technical support and solutions to our customers. The team's core purpose is to ensure customer success and satisfaction by leveraging Synopsys' cutting-edge technologies and products. You will collaborate closely with other engineers, sales teams, and product development teams to achieve our collective goals and drive innovation in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and motivated Senior R&D Engineer with a passion for developing cutting-edge technology solutions. With a background in Computer Science or Electronics and over 6 years of relevant experience, you possess the technical prowess and problem-solving skills needed to excel in this role. Your expertise in C/C++ programming, coupled with a deep understanding of SoC architectures and serial bus protocols, makes you a valuable asset to our team. You thrive in collaborative environments, demonstrate high energy, and are always willing to go the extra mile to achieve project success. Your strong communication skills and ability to prioritize tasks independently allow you to effectively guide junior team members and interact with customers, ensuring the successful delivery of high-quality solutions. What You’ll Be Doing: Contributing to the modeling, integration, and testing of various peripherals within a SystemC-based platform modeling framework for diverse application domains such as Automotive and Wireless. Understanding IP modeling requirements and creating ESL model specifications. Effectively closing open technical issues to ensure project milestones are met. Guiding junior team members and consultants in projects involving SoC platform creation, validation, and software bring-up. Collaborating with cross-functional teams to ensure alignment and integration of virtual prototypes. Staying updated with the latest industry trends and advancements to continuously improve our development processes. The Impact You Will Have: Accelerating early software development and testing use cases for Automotive, Datacenter, AI, and Mobile products. Enhancing the accuracy and efficiency of virtual prototypes, leading to faster product development cycles. Providing critical insights and solutions to complex technical challenges, driving innovation within the team. Improving the overall quality and performance of our SoC modeling and simulation solutions. Supporting the seamless integration of various software applications and operating systems, such as Linux, Android, and AutoSar. Contributing to the success of high-profile projects that shape the future of technology and connectivity. What You’ll Need: BE / B.Tech / M.Tech in Computer Science or Electronics with 6+ years of relevant experience. Proficiency in C/C++ programming. Excellent problem-solving skills. Experience in application development in assembly or higher-level languages. Understanding of SoC architectures and serial bus protocols like CAN, LIN, SPI, I2C (preferred). Experience in SoC peripherals modeling using C/C++/SystemC/HDL (preferred). Experience in multi-core-based platform developments (preferred). Who You Are: A high-energy individual with a willingness to go the extra mile. A team player with strong customer-facing skills. Possess excellent written and verbal communication skills. Demonstrate a high level of initiative and accountability towards assigned tasks. Ability to prioritize and work independently on multiple tasks. The Team You’ll Be A Part Of: You will be part of an excellent development team in the System Level Design space. This team is involved in the creation of Virtual Prototypes (simulation models) for SoCs/MCUs/ECUs and the bring-up of Linux/Android/AutoSar OS/Embedded SW applications. Our focus is on catering to early Software Development & Testing use cases for Automotive, Datacenter, AI, and Mobile products. We collaborate closely to drive innovation and deliver high-quality solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for cutting-edge analog design. Your extensive experience with high-speed interfaces, particularly PCIe 6 and PCIe 7 or SerDes PHY designs, positions you as a technical leader in the field. You possess a deep understanding of transistor-level design and have a proven track record of successfully developing high-speed analog building blocks such as LDOs, Bandgap references, ADC/DAC, PLLs, and DLLs. Your expertise in CMOS technologies, including finFET and SOI processes, and your strong background in jitter budgeting analysis make you an invaluable asset to any team. You are adept at collaborating with cross-functional teams, mentoring junior engineers, and ensuring that designs meet stringent performance, power, and area targets. Your ability to oversee the porting of PHY designs to different technology nodes, while maintaining signal integrity and performance, demonstrates your versatility and commitment to excellence. What You’ll Be Doing: Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys' analog/mixed-signal circuits meet stringent industry standards, enhancing the company's reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the company's design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You’ll Need: PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes. Who You Are: You are a collaborative and innovative problem solver with a keen eye for detail. Your strong communication skills enable you to effectively convey complex technical concepts to both technical and non-technical stakeholders. You are proactive, taking initiative to drive projects forward and overcome challenges. Your passion for continuous learning keeps you at the forefront of technological advancements, and your mentorship helps to cultivate a dynamic and skilled team. The Team You’ll Be A Part Of: You will join a highly skilled and dynamic team of engineers dedicated to pushing the boundaries of analog and mixed-signal design. Our team is focused on developing cutting-edge PCIe PHY designs, ensuring that they meet the highest standards of performance and reliability. Collaboration and innovation are at the core of our team's values, and we thrive on solving complex challenges together. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced R&D Engineering professional with a passion for developing and deploying innovative cloud solutions. You thrive in dynamic environments and are adept at building fullstack solutions utilizing microservices architecture for both public and on-prem cloud infrastructures. Your expertise spans across programming, unit testing, integration testing, and end-to-end testing modules. You are well-versed in quality standards and software development life cycle processes, and you excel at developing DevOps tools and processes for automated CI/CD pipelines. With 2-5 years of experience in cloud infrastructure, you are proficient in programming, particularly with C/C++ on a Linux environment. Your background in cloud deployments, containerization, microservices architectures, and Kubernetes sets you apart. Additionally, you possess excellent debugging and profiling skills for various workloads. What You’ll Be Doing: Developing and deploying innovative cloud solutions in public cloud providers (Azure, AWS, GCP) and/or on-prem. Building fullstack solutions with microservices architecture for both public and on-prem cloud. Programming and developing high-quality unit testing, integration testing, and end-to-end testing modules. Understanding and implementing quality standards and software development life cycle processes. Developing DevOps tools and processes for the automated CI/CD pipelines for developer, QA, and production environments. Collaborating with cross-functional teams to ensure seamless integration and deployment of solutions. The Impact You Will Have: Drive the development and deployment of cutting-edge cloud solutions, enhancing Synopsys' product offerings. Contribute to the efficiency and reliability of our DevOps processes, ensuring smooth CI/CD pipelines. Enhance our software development life cycle processes, leading to higher quality and more reliable products. Support the creation of scalable and robust cloud infrastructure, enabling Synopsys to meet growing market demands. Collaborate with diverse teams, fostering innovation and continuous improvement across the organization. Play a key role in the successful delivery of high-performance silicon chips and software content. What You’ll Need: 2-5 years of experience in building and deploying solutions on public clouds infrastructure. Proficiency in programming, particularly with C/C++ on Linux environment. Good working knowledge and background in cloud deployments, containerization, microservices architectures, and Kubernetes. Experience in developing DevOps tools and processes for automated CI/CD pipelines. Excellent debugging and profiling skills for various workloads. Who You Are: A proactive and innovative thinker with a passion for cloud solutions and software development. A collaborative team player with excellent communication and interpersonal skills. A problem-solver with a keen eye for detail and a commitment to quality. An adaptable and flexible professional, capable of thriving in a fast-paced environment. A continuous learner, always seeking to expand your knowledge and expertise. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team dedicated to developing cutting-edge cloud solutions. Our team focuses on delivering high-performance, scalable, and reliable cloud infrastructure to support Synopsys' product offerings. We collaborate closely with cross-functional teams to ensure seamless integration and deployment, driving continuous improvement and technological innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: Staff Engineer, R&D Engineering Senior R&D Engineer Lead R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a B.Tech in Computer Science and over 6 years of experience in R&D Engineering. You are proficient in system design and data structures and algorithms (DSA) with a knack for problem-solving, code optimization, and debugging. Your expertise lies in programming languages like Python, MySQL, and in developing APIs and web services. You are well-versed in front-end development with React JS and have hands-on experience with Unix and Windows environments. Your background in DevOps tools like Jenkins and CI/CD pipelines is solid, and you have a strong grasp of source control management, particularly with Perforce and GitHub. You thrive in a fast-paced environment where you can work independently with minimal supervision, showcasing your keen attention to detail and excellent communication skills. What You’ll Be Doing: Automating processes using Jenkins and CI/CD pipelines, developing backend and front-end tools, and automating release cycles. Creating and maintaining the infrastructure to support teams in designing, debugging, testing, and releasing products throughout the development cycle. Designing, developing, troubleshooting, and debugging hardware and software solutions. Developing software tools, methodologies, and flows, including operating systems (Linux/Windows), compilers, networks, utilities, databases, and web tools. Integrating and deploying software into production environments. Developing innovative solutions to problems with minimal guidance and implementing them independently. Monitoring infrastructure to ensure service uptime and meeting SLA requirements. Providing critical support for customer-facing services to achieve near 100% uptime. Writing technical and user documentation, including FAQs and handbooks. The Impact You Will Have: Streamlining and automating development processes to increase efficiency and reduce time-to-market. Ensuring robust and scalable infrastructure to support product development and deployment. Enhancing the reliability and performance of our software solutions through innovative problem-solving. Maintaining high service uptime and meeting stringent SLA requirements to ensure customer satisfaction. Contributing to the continuous improvement of development and deployment methodologies. Supporting cross-functional teams by providing the necessary tools and infrastructure for successful project execution. What You’ll Need: B.Tech in Computer Science with 6+ years of experience in R&D Engineering. Proficiency in system design and data structures and algorithms (DSA). Strong programming skills in Python, MySQL, APIs development, and web services. Experience in front-end development with React JS. Hands-on experience with Unix and Windows environments. Expertise in DevOps tools such as Jenkins and CI/CD. Experience in source control management, particularly with Perforce and GitHub. Ability to work independently with minimal supervision and keen attention to detail. Excellent verbal and written communication skills. Who You Are: You are a detail-oriented and self-motivated professional with a strong technical background. Your problem-solving skills are exceptional, and you have a proven ability to develop innovative solutions independently. You excel in a collaborative environment, effectively communicating with both technical and non-technical stakeholders. Your ability to multitask and manage multiple projects simultaneously sets you apart, and you are committed to achieving operational goals with a direct impact on your area of work. The Team You’ll Be A Part Of: You will join a dynamic and innovative team focused on developing cutting-edge solutions in the field of R&D Engineering. Our team values collaboration, creativity, and continuous improvement, working together to drive technological advancements and achieve excellence in all aspects of product development and deployment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team Experience in design of Charge-pump PLLs, Fractional-N PLLs, DLL design techniques, LDO design techniques Hands-on experience on designing charge pumps, LC VCOs, Ring oscillators, phase interpolator, bandgap reference, etc. In depth familiarity with transistor level circuit design at SPICE netlist level and should be capable to develop SPICE verification testbench Design exposure in advanced process nodes (FinFETs) Hands on experience with industry standard tools (Cadence, Synopsys, Mentor) for schematic capture spice simulations. Familiarity with automation / Scripting language (TCL, Python, PERL). Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of device mismatch and proximity effects. understanding of ESD issues and reliability issues Looking for 1-2 years of experience in Analog design with master's degree or 2-4 years of experience in in Analog design with bachelor's degree In depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the PLL within Highspeed SerDes Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced Layout Design Engineer with a strong background in transistor level analog and mixed signal layout. You thrive in dynamic environments and possess a deep understanding of device-level floor planning, placement, routing, and physical verification processes. You excel at troubleshooting and resolving physical verification issues to achieve clean and desired results. Your ability to create and review layout documents ensures that quality standards are met, and deliverables are on time. You are passionate about learning and exploring new techniques, and you effectively communicate with cross-functional teams to ensure successful project execution. With a strong foundation in electrical and electronic fundamentals, semiconductor device physics, and CMOS fabrication technology, you bring valuable expertise to the team. What You’ll Be Doing: Design and develop transistor-level analog and mixed signal layouts. Perform device-level floor planning, placement, routing, and physical verification. Troubleshoot and resolve physical verification issues to achieve clean results. Create and review layout documents to ensure they meet quality standards and deadlines. Plan, estimate, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Stay updated with the latest techniques and tools in custom mixed signal layout flows. The Impact You Will Have: Ensure the successful design and development of high-performance analog and mixed signal layouts. Contribute to the overall quality and reliability of our products through meticulous layout design and verification. Help Synopsys maintain its leadership in the semiconductor industry by delivering cutting-edge technology solutions. Support cross-functional teams in achieving project goals and milestones. Enhance the efficiency and effectiveness of our layout design processes through continuous improvement. Drive innovation and excellence in layout design, contributing to the advancement of our technology offerings. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. Minimum 6+ years of experience in Analog and Mixed Signal Circuit Layout. Experience with Analog Layout Flow from Device placement to GDS release. Strong knowledge of Electrical and Electronic fundamentals, Semiconductor device physics, CMOS, and FINFET technologies. Proficiency in EDA tools for custom mixed signal layout flows. Who You Are: Self-directed and detail-oriented with excellent problem-solving skills. Effective communicator with the ability to collaborate with cross-functional teams. Passionate about learning and exploring new techniques. Capable of planning, estimating, scheduling, and executing tasks in a multi-project environment. Knowledgeable about electro migration, reliability concepts, ESD/LUP concepts, and their application in layout design. The Team You’ll Be A Part Of: You will be a part of a dynamic and innovative team focused on the design and development of high-performance analog and mixed signal layouts. Our team collaborates closely with cross-functional teams to deliver cutting-edge technology solutions that meet the highest quality standards. Together, we drive the continuous improvement of our layout design processes and contribute to the advancement of Synopsys' technology offerings. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What You'll Be Doing In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What We Need To See BE/BTECH/MTECH, or equivalent experience. 4+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. JR1996348 Show more Show less

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-5 years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of experience in Design Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Summary This position is open for 2-10 years experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for custom design . Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IPs being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams. Job Responsibilities Job responsibilities include design and development of custom macro using Schematic design at block level (Ex RegArray, memory subsystem) Frontend verification and model generations CLP/PAGLS/LEC verifications at block level. Functional verification using spice/gatesim. Timing Signoff using PT, Candidate should be able to collaborate with different teams. Skillset/Experience 2-10 year of experience: Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path. STA for the design to close Set-up, Hold, MPW, Transition, etc Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE. Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX) Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter. Scripting in Perl/Python/Shell/Tcl for productivity is a plus IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification. Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries Implement block level floor planning using custom and/or tiling techniques Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ Year of industry experiences in the following areas Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus. o"ƒHands on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs. o"ƒExpertise in formal verification with Cadence LEC/ Synopsys Formality o"ƒExpertise in writing and debugging timing constraints o"ƒPerl and/or TCL scripting, makefile flows. Qualcomm's compute sub system engineers will work on next generation low power, machine Learning sub-system for our system-on-chip (SoC) products used in Smartphone, Automotive and other low power devices. Become a key member of the core team developing fastest smartphone SoC devices implemented on the latest cutting-edge process technologies. In this role candidate will be responsible for compute sub system implementation that includes Physically aware Synthesis -DCG/Fusion Compiler/Genus. In addition, he/she will perform tasks toward constraints development, clock definitions, timing analysis, UPF, CLP check, Formal Verification and ECO flow. He/She will be working closely with physical Design team to optimize designs for power, area, and performance. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Description: We are urgently seeking an experienced and passionate VLSI Trainer to deliver high-quality training sessions in VLSI Design and Verification. The ideal candidate will be responsible for designing curriculum content, conducting interactive theoretical and hands-on sessions, and mentoring students on real-world projects using industry-standard EDA tools. Key Responsibilities: ✅ Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. ✅ Prepare, update, and structure course materials and assignments as per industry standards. ✅ Conduct practical sessions using tools such as Cadence, Synopsys, Mentor Graphics, or equivalent. ✅ Evaluate student performance through assignments, projects, and assessments. ✅ Provide constructive feedback and personalized guidance to enhance learning outcomes. ✅ Keep abreast of emerging trends and advancements in the semiconductor/VLSI domain. Required Qualifications: 🎓 Bachelor's or Master's degree in Electronics, Electrical, or Communication Engineering or a related field. 💡 Hands-on experience in VLSI Design and/or Verification. 🛠️ Proficiency in industry-standard VLSI EDA tools (Cadence, Synopsys, Mentor Graphics, etc.). 🗣️ Strong communication skills with a passion for teaching and mentoring. 📚 Familiarity with current training methodologies, curriculum development, and evaluation techniques is a plus. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. Job Description: Full chip design for multi million gates SoC Digital design and development (RTL) Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Manage IP dependencies, planning and tracking of all front end design related tasks Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: Minimum 15 years of solid experience SoC design Developing architecture and micro-architecture from specs Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC Understanding of Memory controller designs and Microprocessors is an added advantage Understanding of Chip IO design and packaging is an added advantage Familiarity with various bus protocols like AHB, AXI is highly desired Ability to review top level test plans Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC Working knowledge of timing closure is a must Should have good post silicon bring up and debug experience Should have good SoC integration exposure and its challenges Should have good exposure to design verification aspects Having SoC specification to GDS to commercialization experience is highly desired Needs to makes effective and timely decisions, even with incomplete information. Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas. Provides direction, mentoring, and leadership to a small to medium sized groups. Should possess strong communication and leadership skills to ensure effective communication with Program Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073214 Show more Show less

Description : We are looking for a highly skilled and motivated engineers to join the team that is modelling ARM’s v9 architecture and the latest RISC-V cores from our customers in the RISC-V ecosystem. You will create C software models of leading-edge CPU technologies that will power future systems in markets such as data centers, mobile communications, and Internet of Things (IoT). You will be joining an experienced multinational development team located in UK, Europe, or USA. The team is responsible for building and supporting high speed simulation models of Arm and RISC-V processors and embedded systems. These models are for use in IP design, verification, and software development, and are also delivered to our OEM and Silicon Partners. The models are distributed with configuration and analysis tools, and can be integrated into standard SystemVerilog, C, C++, and SystemC environments. Job Purpose : As part of the modelling team, you will build highly efficient C models and platforms using the industry open standard OVP APIs, as well as working with other teams to design systems to allow our Imperas Fast Processor Models to be used within their workflows and platforms. Key objectives of this role include: To develop, test, and maintain high speed software models (ImperasFPMs) of advanced CPU and system level IP. To technically support other engineers. To be responsible for producing and executing model development plans for your area of responsibility, in conjunction with project management and engineering peers. To build Virtual Platforms that can be used for early software development. To support internal and external users of these CPU models. We offer an international work environment that is characterized by flexibility, an informal atmosphere, a fast pace and an opportunity to impact the way the industry develops new systems and embedded software. You will work with highly professional and motivated colleagues who value and support your contribution. Synopsys is a dynamic international workplace with opportunities for personal and professional growth. The position carries an attractive compensation and benefits package commensurate with a competitive global company. Technical attributes: Mandatory: Bachelors/Masters in ECE/CS with 5+ years of experience Excellent in C/C++ Knowledge of Processor architectures – Arm, RISC-V etc Knowledge of Hardware and Software Interfacing Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills Preferred: Knowledge of SystemC, TLM and experience creating system level models Knowledge of Embedded Software Understanding of Peripheral model internals or Interconnects like AXI / AHB Experience with EDA Tools Show more Show less

Applications Engineer (AE) Alternate Job Titles: IP Applications Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and passionate Applications Engineer, ready to join our dynamic team. You thrive in fast-paced environments and are driven by the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI®) domain. With your strong technical background in ASIC design, you are adept at providing top-tier technical support and guidance. Your excellent communication skills enable you to effectively interact with customers and internal teams alike. You are not just looking for a job, but a place where you can make a significant impact and grow your career. What You’ll Be Doing: Providing technical support to field engineers and customers utilizing Synopsys’ MIPI UFS Intellectual Property (IP) Partnering with high-tech customers through the full cycle of ASIC design, from installation and training to RTL design and production testing Conducting reviews on customers' major SoC design milestones Authoring application notes and white papers to promote the IPs’ ease of use and address specific challenges Providing feedback to internal teams for continuous product improvements based on customer feedback Ensuring successful integration of Synopsys MIPI IP solutions into customers' SoCs The Impact You Will Have: Enhancing customer satisfaction by providing expert support and ensuring seamless integration of Synopsys IP Driving innovation by collaborating with customers on cutting-edge SoC designs Contributing to the development of industry-leading IP solutions through continuous feedback and improvement processes Expanding Synopsys' market presence in the MIPI domain through successful customer engagements Promoting the adoption of Synopsys IP by authoring impactful documentation and white papers Supporting the growth of Synopsys' IP portfolio by identifying and addressing customer needs What You’ll Need: Bachelor’s degree with 5+ years or Master’s degree with 2+ years of relevant experience in the ASIC design process Proficiency in Verilog HDL, synthesis, simulation, and verification Knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous Experience with Synopsys tool suites is a plus Strong verbal and written communication skills in English Who You Are: An excellent communicator with the ability to interact effectively with customers and internal teams A problem solver who thrives in a dynamic environment A collaborative team player with a customer-centric approach Detail-oriented with strong analytical skills Passionate about technology and continuous learning The Team You’ll Be A Part Of: You will join a dedicated and innovative Applications Engineering team, focused on supporting our customers in the Synopsys Intellectual Property (IP) domain. Our team is committed to excellence, working collaboratively to drive customer success and advance the capabilities of Synopsys IP solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a dedicated and experienced Site Reliability Engineer, you thrive in a dynamic and collaborative environment. You possess a deep understanding of IT infrastructure and the intricacies of ensuring its reliability, performance, and scalability. Your extensive experience with a wide range of infrastructure technologies, including Linux, Windows, and cloud computing, sets you apart. You are adept at troubleshooting complex issues, developing automated solutions, and continuously improving processes. Your passion for innovation drives you to challenge the status quo and optimize existing procedures. With excellent problem-solving skills and the ability to work through challenges, you are ready to make a significant impact on our engineering excellence. Your communication skills, both verbal and written, are exceptional, allowing you to collaborate effectively with cross-functional teams. You are proactive, resourceful, and have a strong service availability-oriented mindset. What You’ll Be Doing: Discovering, designing, and implementing changes to existing IT infrastructure to improve reliability, performance, and standardization. Collaborating with engineering and business units to translate customer, business, and technical requirements into SRE practices and enhancements. Ensuring efficient resource utilization and continuously improving processes through automation and internal tools. Troubleshooting production issues, providing root cause analysis, and designing solutions to prevent future occurrences. Monitoring services and creating intelligent alarming for quicker incident detection and resolution. Maintaining vulnerability management processes and policies using a risk-based priority methodology. Collaborating with various teams and platform owners on all vulnerability management and reporting. Applying architectural and infrastructure disciplines to solve business problems strategically. Participating in off-hours maintenance activities and being part of the on-call rotation schedule. The Impact You Will Have: Enhancing the reliability and performance of Synopsys' IT infrastructure. Driving significant productivity, robustness, agility, and time-to-market advantages in the creation of Synopsys products and solutions. Leading corporate infrastructure transformation and IT operations leadership. Implementing automation and internal tools to improve service delivery, maturity, and scalability. Reducing production issues through effective troubleshooting and root cause analysis. Ensuring proactive monitoring and quicker incident detection and resolution. What You’ll Need: Extensive experience with infrastructure technologies such as Linux, Windows, cloud computing, virtualization, and containerization. Deep understanding of IT infrastructure services and their dependencies. Experience with administration, security hardening, and performance tuning of Linux and Windows OS. Experience with developing service level indicators and objectives, and building alerts. Proficiency in ITIL processes and frameworks. Hands-on experience with infra-automation tools like GitHub, Jenkins, Terraform, and Ansible. Experience with one or more programming languages such as Java, Python, Go, or NodeJS. Who You Are: Proactive and resourceful with a service availability-oriented mindset. Excellent problem-solving skills and ability to work through challenges. Strong communication skills, both verbal and written. Passionate about innovation and optimizing existing processes. A team player who can collaborate effectively with cross-functional teams. The Team You’ll Be A Part Of: The Engineering Excellence Group drives innovation velocity and enterprise infrastructure automation, which are critical elements of our growth and scaling strategy. This team is chartered to drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. The group also leads corporate infrastructure transformation as we continue to drive IT operations leadership and invest in the next wave of disruptive technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a minimum of 12 years of experience in analog and mixed signal circuit layout design, including at least 5 years of people management experience. You possess a deep understanding of electrical and electronic fundamentals, particularly in the context of FinFET nodes. Your expertise in EDA tools for custom mixed signal layout flows is unparalleled, and you have a proven track record of designing high-speed SERDES blocks. You are adept at troubleshooting physical verification issues and ensuring the delivery of high-quality, reliable silicon chips. Your leadership skills enable you to mentor and retain a diverse team of experienced layout designers, driving innovation and excellence in your projects. What You’ll Be Doing: Plan, estimate area/time, schedule, delegate tasks, and execute to meet project milestones in a multi-project environment. Communicate effectively with cross-functional teams for successful project execution. Create and review layout documents to ensure they meet quality standards and are delivered on time. Hire, mentor, and retain a mixed blend of experienced layout team members. Design and develop transistor to macro level analog and mixed signal layout, particularly for high-speed SERDES blocks. Perform device level floorplanning, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. The Impact You Will Have: Contribute to the design and development of high-performance silicon chips. Ensure the reliability and functionality of analog and mixed signal layouts. Drive innovation by applying advanced knowledge of semiconductor technologies. Enhance the quality and efficiency of layout design processes. Support the successful delivery of projects within tight deadlines. Collaborate with multidisciplinary teams to achieve organizational goals. What You’ll Need: Minimum 12 years of experience in analog and mixed signal circuit layout, including at least 5 years of people management experience. Hands-on experience in complete analog layout flow from floorplanning and device placement to GDS release. Strong knowledge of electrical and electronic fundamentals, especially in FinFET node technologies. Proficiency in EDA tools for custom mixed signal layout flows. - In-depth knowledge of FinFET rules, constraints, and techniques to mitigate parasitic effects. Strong understanding of electromigration, ESD, and LUP fundamentals, with skills in analyzing EMIR, ESD PERC, and ESD CNOD results. Experience in product release flow and quality checks. Who You Are: A proactive leader with excellent communication and mentoring skills. Detail-oriented and committed to delivering high-quality results. Innovative and capable of driving technological advancements. Collaborative and able to work effectively with cross-functional teams. A problem-solver with strong analytical skills. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved. Key Requirements Experience: Bachelor’s degree in Electronics with 7+ Years’ or Master’s degree in Electronics with 5+ Years' Experience in verification technologies (Simulation, UVM, SVA, LRM understanding) Strong HDL language support (Verilog, VHDL, System Verilog) Simulation, UVM, Design Verification Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting – Perl, TCL, Make, Shell Scripting. Role - VCS Simulation Technology Product Engineer Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective Team player, partners with multiple stakeholders, has attention to detail and innovative mindset Motivated, doer and self-organized team worker with good social communication skills Open to travel, ability to multi-task, be detail-oriented Drive VCS/related technology customer deployment working closely with field and R&D Drive competitive engagements, requirements gathering for delivery strong product roadmap Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues At Synopsys, we’re at the heart of the innovations that positively impact the world. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you echo our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated TCAD Calibration Workflow Engineer with a robust background in developing and optimizing semiconductor simulation models. With a strong foundation in Python programming and experience in TCAD simulation, you excel in creating efficient calibration workflows that enhance performance while maintaining accuracy. Your collaborative nature allows you to work seamlessly with cross-functional teams, including product application engineering (PAE) and front-end development teams, to deliver intuitive and effective solutions for our customers. You thrive in a dynamic, international environment and are eager to learn and apply new technologies to advance our calibration strategies. Your ability to communicate complex technical concepts clearly and effectively makes you an invaluable asset to our team. What You’ll Be Doing: Collaborate with the PAE team to build, debug, and optimize topography calibration workflows using SCW, focusing on deposition processes. Design and implement scalable calibration strategies by reducing simulation complexity while maintaining accuracy, aiming to reduce Turnaround Time (TAT) and manage a large number of calibration parameters efficiently. Identify and develop techniques to simplify TCAD model complexity to accelerate calibration workflows and implement quick fine-tuning techniques to meet stringent customer accuracy expectations. Enhance SCW integration with underlying TCAD simulation tools to improve automation, scalability, Quality of Results (QoR), and Ease of Use (EoU), and reduce TAT. Collaborate closely with the front-end team to ensure backend features are seamlessly integrated into the GUI for end-users. Support debugging TCAD simulations Design of Experiments (DoE) and interface with the PAE team to define best practices in physical model selection and parameter calibration. The Impact You Will Have: Drive advancements in TCAD calibration workflows, leading to significant improvements in simulation efficiency and accuracy. Enhance the user experience by integrating backend features into a user-friendly GUI, enabling seamless deployment of calibration workflows to customers. Contribute to the development of industry-leading calibration strategies that set new standards for performance and reliability. Support the creation of innovative solutions that address complex semiconductor design challenges, contributing to the success of our customers. Streamline the calibration process, reducing TAT and improving overall productivity for both internal teams and customers. Foster collaboration and knowledge sharing within the team, driving continuous improvement and innovation in our calibration workflows. What You’ll Need: MS or PhD in Computer Science, Software Engineering, Electrical Engineering, or equivalent. 3+ years of hands-on experience in software development with solid programming skills in Python. Experience with TCAD simulation and semiconductor domain knowledge (physics and applications). Strong desire to learn and explore new technologies. English language working proficiency and communication skills allowing teamwork in an international environment. Willingness to work in a distributed international team. Who You Are: You are a proactive and innovative engineer with a passion for technology and a keen eye for detail. Your strong analytical skills enable you to solve complex problems efficiently, and your collaborative spirit ensures successful teamwork across diverse teams. You are adaptable and open to learning, always seeking to enhance your skills and contribute to the team's success. With excellent communication skills, you effectively convey technical concepts and foster a positive and productive work environment. The Team You’ll Be A Part Of: You will join the Sentaurus Calibration Workbench (SCW) team, a dynamic group of experts dedicated to developing and optimizing calibration workflows for TCAD topography simulation models. Our team collaborates closely with the product application engineering (PAE) team and front-end developers to deliver cutting-edge solutions that meet the evolving needs of our customers. We are committed to continuous innovation and excellence, driving advancements that shape the future of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned technical writer with a passion for making complex information accessible and engaging. With a keen eye for detail and a deep understanding of technical writing standards, you excel in creating comprehensive and clear documentation for highly technical audiences. You thrive in fast-paced environments, and your ability to learn new technologies quickly sets you apart. Your excellent communication skills enable you to collaborate effectively with engineers, designers, and other stakeholders, ensuring that the documentation you produce meets the highest standards of quality and usability. You have a strong background in engineering or science, with a Bachelor’s or Master’s degree to support your technical expertise. With 5 to 12 years of experience in technical writing within a software product development company, you bring a wealth of knowledge and best practices to the role. Your proficiency in DITA and XML authoring tools, as well as your familiarity with UNIX or Linux, make you an invaluable asset to the team. Additionally, your experience with electronic design automation (EDA) tools gives you a unique perspective that enhances your ability to create relevant and impactful documentation. What You’ll Be Doing: Developing and maintaining documentation for EDA products used by chip designers and scientists. Planning, organizing, and creating user guides, reference material, and release notes for design engineering audiences. Researching and organizing initial source material into high-quality drafts, including product specifications, training materials, and engineering input. Collaborating with Applications and R&D engineers to solicit feedback and reviews. Implementing good standard writing practices to develop clear and concise technical content. Ensuring documentation is up-to-date with the latest product releases and features. The Impact You Will Have: Enhancing the usability and adoption of Synopsys products through clear and comprehensive documentation. Supporting the success of chip designers and scientists by providing them with the information they need to effectively use Synopsys tools. Improving customer satisfaction by addressing their requirements through well-crafted documentation. Contributing to the overall quality and reliability of Synopsys products by ensuring accurate and detailed documentation. Facilitating better communication and collaboration between engineering teams and end-users. Helping to drive continuous improvement in documentation processes and standards. What You’ll Need: Bachelor’s or Master’s degree in Engineering or Science. 5 to 12 years of technical writing experience in a software product development company. Good knowledge of technical writing standards and processes. Ability to grasp new technology quickly. Excellent written and verbal communication skills. Experience with DITA and XML authoring tools such as Oxygen XML Author. Working knowledge of UNIX or Linux. Experience with electronic design automation (EDA) tools. Who You Are: A detail-oriented professional with a passion for technical writing. A quick learner who adapts easily to new technologies and processes. An excellent communicator who can convey complex information clearly and effectively. A team player who collaborates well with engineers and other stakeholders. A proactive problem-solver who can make decisions quickly and reprioritize tasks as needed. The Team You’ll Be A Part Of: You will join a dynamic team dedicated to developing and updating product documentation for Synopsys product releases. This team includes experienced technical writers, engineers, and product managers who work collaboratively to create high-quality documentation that meets the needs of our highly technical audience. Together, you will contribute to the success of Synopsys products by ensuring that users have access to clear, accurate, and comprehensive information. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process....Less Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced Layout Design Engineer with a strong background in Analog and Mixed Signal Circuit Layout. You thrive in a dynamic environment where you can apply your in-depth knowledge of semiconductor device physics, CMOS and FINFET technologies, and EDA tools. Your meticulous attention to detail and problem-solving skills enable you to troubleshoot and resolve physical verification issues effectively. You are a proactive learner, eager to explore new layout techniques, and possess excellent communication skills to collaborate seamlessly with cross-functional teams. With a minimum of 3 years of relevant experience, you are ready to take on new challenges and contribute to delivering high-quality layout designs on time. What You’ll Be Doing: Design and development of Transistor level analog and mixed signal layout. Device/block level floorplan, placement, routing, and physical verification. Troubleshoot Physical verification issues to get clean and desired results. Create and review layout documents to ensure they meet quality standards and are delivered on time. Collaborate with cross-functional teams to optimize layout designs for performance and manufacturability. Stay updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Ensure the delivery of high-quality and reliable layout designs that meet project timelines. Contribute to the development of cutting-edge technologies in chip design and verification. Enhance the performance and efficiency of analog and mixed signal circuits through meticulous layout design. Play a key role in troubleshooting and resolving physical verification issues, ensuring clean and desired results. Collaborate with cross-functional teams to drive innovation and continuous improvement in layout design processes. Help maintain Synopsys' reputation as a leader in the semiconductor industry through high-quality layout design contributions. What You’ll Need: Bachelor's or master's degree in Electrical Engineering or a related field. Minimum of 3 years of experience in Analog and Mixed Signal Circuit Layout. Expertise in Analog Layout Flow from Device placement till GDS release. In-depth knowledge of semiconductor device physics, analog circuits, and CMOS/FINFET technologies. Proficiency in EDA tools for Custom Mixed signal layout flows. Strong understanding of CMOS Fabrication technology, deep sub-micron effects, and their impact on layout. Knowledge of EMIR, ESD, LUP, Cross talk, Shielding, and their impact on design. Experience in Tcl is a plus. Who You Are: A proactive and self-directed individual with a passion for learning and exploring new layout techniques. Detail-oriented with excellent problem-solving skills. Strong communicator with the ability to collaborate effectively with cross-functional teams. Adaptable and able to thrive in a fast-paced, dynamic environment. Committed to delivering high-quality work and meeting project deadlines. The Team You’ll Be A Part Of: You will be part of a highly skilled and collaborative team dedicated to designing and developing high-performance analog and mixed signal layouts. The team focuses on innovation, continuous improvement, and delivering exceptional results. You will work closely with other layout designers, circuit designers, and verification engineers to ensure the successful delivery of projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less