1771 Synopsys Jobs - Page 15

Job Description Experience with low-power ASIC design techniques and clock domain crossing Knowledge of AMS verification methodologies Exposure to silicon bring-up and lab validation Familiarity with EDA tools from Synopsys, Cadence, or Mentor Key Responsibilities HOW YOU WILL CONTRIBUTE AND WHAT YOU WILL LEARN Lead the architecture, design, and verification of digital blocks for mixed-signal ASICs Collaborate closely with Analog and System teams to define specifications and ensure seamless integration Drive RTL design using Verilog/SystemVerilog and optimize for power, performance, and area Follow the digital design flow from concept to tape-out, including synthesis, static timing analysis ...

DV lead/manager www.sevyamultimedia.com Hyderabad About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC DV lead/manager to verify IP/SoC using System Verilog/UVM --------------------------------------------------------------------------------...

We are looking for a skilled professional with 05-20 years of experience to join our team as a (VLSI) Physical Design (PD) expert in Bangalore, Hyderabad, Kochin, and Pune. The ideal candidate will have hands-on experience with Netlist2GDSII Implementation, including floor planning, placement, CTS, routing, STA, power integrity analysis, physical verification, and programming in Tcl/Tk/Perl. Roles and Responsibility Implement Netlist2GDSII for various projects. Perform floor planning, placement, CTS, routing, STA, and power integrity analysis. Conduct physical verification and ensure successful project delivery. Collaborate with cross-functional teams to meet project goals. Develop and maint...

We are looking for a skilled professional with 7 to 15 years of experience in Design Verification to join our team. The ideal candidate will have expertise in SV/UVM Test Bench Development and protocols such as PCI Express, UCIe, CXL, AXI, ACE, CHI, Ethernet, RoCE, RDMA, DDR, LPDDR, or HBM. Roles and Responsibility Develop and implement test benches using SV/UVM methodology. Collaborate with cross-functional teams to identify and prioritize verification requirements. Create and execute test cases to ensure design quality and reliability. Analyze and debug issues found during testing. Participate in the development of verification plans and strategies. Work closely with designers to resolve d...

We are looking for a skilled ASIC / RTL Design Professional with 7 to 15 years of experience. The ideal candidate will have expertise in RTL, Coding, Design, IP Design, SOC Development, Lint, CDC, and Micro Architecture. Roles and Responsibility Design and develop high-quality ASICs using RTL design principles. Collaborate with cross-functional teams to ensure successful project execution. Develop and implement coding standards for efficient code generation. Participate in IP design and SOC development activities. Troubleshoot and debug issues related to Lint, CDC, and Micro Architecture. Ensure compliance with industry standards and best practices. Job Requirements Strong knowledge of RTL, ...

Design Verification Engineer - Specialised in Protocol like;n PCIe/Ethernet/DDR/LPDDR/HBM Location: Bangalore, India Experience: 5-12 Years Job Description Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level. Skills: Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL...

Education Requirements B. Tech / M. Tech (ECE) Experience 3 to 13 Years Job Location Hyderabad Shift General (No WFH) Work Week Monday to Friday He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. · Provide technical guidance, mentoring to physical design engrs. · Interf...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

Position: Design Verification- Manager Engineering Experience: 12+ years relevant experience. Location - Bangalore/Hyderabad/Chennai/Noida Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced verification languages and methodology. The person would be working with experienced and motivated team of Designers and Verification resource and able to address the verification challenges in the context of the IP, Subsystem, and overall system, using simulation and formal verification and actively participate...

Responsibilities: Collaborate with cross-functional teams on project deliverables. Optimize timing closure through innovative techniques. Perform physical verification using Synopsys tools.

Job Requirements Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow Analyze timing report and suggest for the solutio...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature -Leading junior teams, Mentori...

- Should have worked hands-on ASIC DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at Lower nodes ; 14nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team w...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MI...

Job Description 8+ years of hands-on ASIC DFT experience with multiple production tapeouts owning full-chip DFT. Proven ownership of MBIST architecture and hands-on insertion across large memory arrays; experience with repair, redundancy, and BIRA/BISR flows. Hands-on scan insertion and compression, ATPG pattern generation and coverage closure. Solid understanding of test-mode timing, constraints, and PnR interactions; experience with test clocks/reset distribution and power intent in test modes. Proficiency with at least one major DFT tool suite : Synopsys (DFTMAX/SpyGlass-DFT/TetraMAX), Siemens Tessent (Scan/MBIST/ATPG), or Cadence Modus. Experience with JTAG/boundary scan and, ideally, IE...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job description DFT Engineer Experience: 6+ Years Location: Pune & Banglore Required skills 1. Expertise in MBIST, Scan Insertion, DRC analysis & resolution, ATPG, and simulations for ASICs. 2. Experience with IOBIST (SerDes verification) and BIST sequence simulations for ASICs. 3. Strong knowledge in test coverage improvement and hierarchical test methodologies . 4. Proven debugging skills with complex designs. 5. Hands-on experience with Synopsys DFT tool suite TestMax Manager, TestMax ATPG, TestMax Advisor, and VCS. 6. Familiarity with Physical Design (PD) and Timing collaterals .

About The Role Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Colla...

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own ...