906 Synopsys Jobs - Page 16

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics PREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in block level NOC (Net work on Chip) verification is a plus. Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Category Information Technology Hire Type Employee Job ID 9009 Remote Eligible No Date Posted 29/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a talented, energetic, and experienced individual with a passion for Linux administration and cloud operations. With a strong foundation in Azure fundamentals, you excel in maintaining high-performance cloud environments. Your ability to communicate effectively, make practical decisions, and deliver agile goals sets you apart. You bring a wealth of experience in customer support, systems administration, and network operations, making you an ideal candidate for our team. You thrive in a dynamic environment, adept at multitasking and problem-solving, and you are ready to take on the challenge of ensuring the smooth operation of Synopsys Cloud. Your hands-on experience with UNIX system administration, coupled with your proficiency in scripting languages like Shell and Python, makes you a critical asset to our operations support team. What You’ll Be Doing: Design, automate, and support Linux systems and services in a 24*7 production environment. Work both independently and collaboratively to evaluate, recommend, and implement technical solutions that meet business needs. Collaborate with other technical teams to solve problems and continually evolve the technology landscape. Troubleshoot issues to identify root causes and help unblock the customer. Prepare and maintain comprehensive documentation of systems, standards, configurations, and procedures. Support day-to-day operations, including installation, configuration, maintenance, and troubleshooting of the engineering secure computing environment. The Impact You Will Have: Ensuring the high performance and reliability of the Synopsys Cloud environment. Contributing to the seamless operation and security compliance of our cloud infrastructure. Enhancing the efficiency and effectiveness of our technical solutions through continuous evaluation and implementation. Collaborating with cross-functional teams to drive innovation and solve complex technical challenges. Providing critical support and troubleshooting to maintain uninterrupted services for our customers. Maintaining up-to-date documentation to ensure consistency and compliance across our systems. What You’ll Need: Extensive knowledge of Linux operating systems and security patching. Experience in installing, monitoring, and administering Linux systems (Ubuntu and RHEL primarily). One or more Linux System Administrator Certifications. Proficiency with monitoring and logging tools. Strong programming/scripting skills in Shell/Python. Who You Are: Proficient in basic networking fundamentals, including TCP/IP, DNS, subnetting, and routing. Knowledgeable in networking for virtual machines, particularly regarding security and performance. Experienced with remote desktop software solutions, such as VNC, Citrix Xen server, and VDI. Solid understanding of infrastructure services like Kickstart, NFS, DNS, and DHCP. Familiar with Azure resources like VM, Network, NSG, and Blob Storage. Able to communicate technical concepts clearly to both technical and nontechnical users. Proven ability to work collaboratively in a dynamic team environment to resolve complex problems. Enthusiastic and capable of learning on the job. The Team You’ll Be A Part Of: Our team is dedicated to building, operating, and maintaining a high-performance Synopsys Cloud environment. We focus on ensuring smooth operations, compliance with security policies, and driving continuous innovation. You will work alongside a group of highly skilled professionals who are passionate about technology and committed to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Site Reliability Engineering, Sr Staff The Engineering Excellence Group drives innovation velocity and enterprise infrastructure automation, which are critical elements of our growth and scaling strategy. This team is chartered to drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. The group also leads corporate infrastructure transformation as we continue to drive IT operations leadership and invest in the next wave of disruptive technologies. Key Roles & Responsibilities Discover, design, implement changes to existing IT infrastructure with the focus of improved reliability, performance, and standardization. Collaborate with Engineering and business units to translate customer, business, and technical requirements into SRE architectural designs and enhancements. Ensure efficient resource utilization and continuously improve processes leveraging automation and internal tools resulting in enhanced service delivery, maturity, and scalability. Troubleshoot production issues providing root cause analysis and designing solutions to prevent future occurrences. Monitoring of services and creating intelligent alarming for quicker incident detection and resolution. Maintain vulnerability management processes and policies using a risk-based priority methodology. Collaborate with the various teams and platform owners on all vulnerability management and reporting. Mentor and coach other SRE team members. Strategically apply architectural and infrastructure disciplines to solve business problems. Participate in an on-call rotation. Required Skills Extensive experience with a wide range of infrastructure technologies, such as but not limited to Linux, Windows, High-performance computing, storage platforms, networking, cloud computing, cloud services (IaaS, PaaS, SaaS, etc.), virtualization, OpenStack, containerization, and orchestration technologies (e.g., Docker, Kubernetes). Solid understanding of the underpinnings of container technology such as Cgroups and Namespaces. Deep understanding of IT infrastructure related services and their dependencies required to troubleshoot issues and define mitigations. Solid experience with the administration, security hardening, and performance tuning of Linux and Windows OS. In-depth knowledge of CIS benchmarking standards. Experience with developing service level indicators and objectives, instrumenting software, and building alerts. An understanding of software engineering fundamentals with experience developing software with a team of engineers. Strong experience in the practice of testing. Experience with the operations, administration, and development of orchestration systems such as Kubernetes, ECS, Mesos. Passion for tracking down technical root causes of distributed systems, and software. Experience with ITAM, Service Mapping, and CMDB (service-now) Strong technical foundation, with the ability to engage deeply on technical topics related to data center and cloud infrastructure, software reliability, and operational practices. Proficiency in ITIL (Information Technology Infrastructure Library) processes and frameworks Service availability-oriented mindset with a pro-active approach to problem solving. An ideal candidate should be able to develop automated solutions to prevent recurring problems. Possesses the ability and willingness to challenge the status-quo and optimize current processes and procedures. Experience & Education Masters/bachelor’s degree with minimum of 12+ years of experience in IT infrastructure & operations with 6+ years in an SRE role 12+ years of experience with infrastructure architecture design, implementation, and support in large organizations. Implementation experience in infra-automation tools and frameworks like GitHub, Maven/Gradle, Jenkins, Terraform (IaC), Ansible, Shell scripting. Hands on experience with one or more of Java/Python/Go/NodeJS languages. Well versed with SDLC, Agile processes and CI/CD tools. Well versed with ITIL process including incident, request and change management. Strong understanding of cloud, automation, networking and SIEM tools. Excellent verbal and written communication skills Excellent problem-solving skills and ability to work through issues and challenges. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Position: Pre-Post Silicon Embedded Engineer Years of Experience: 10+ Years Location: Bengaluru, Karnataka Job Brief: Today, software is proliferating in every sector. Automotive, HPCs, Consumer electronics, etc. Name any domain, and you will notice huge lines of software code. It’s fair to say that soon, software will rule the world. One of the big challenges for system and silicon companies is to verify and validate their SoCs as early in the product design cycle as possible. Product teams are achieving this by performing what is called a “ shift left ”. In the context of chip verification and validation, it is tantamount to having device drivers/software. Engineers work as part of silicon validation teams and develop driver software to test the SoC, all its critical data paths, performance et al during pre-silicon verification itself. Job Description: Vayavya Labs is closely working with an industry leader in the consumer electronics space for the development of a device driver and bare metal software to verify and validate the customer’s cutting edge SoC. The job involves working with the pre- & Post silicon bringup teams. Understanding the SOC architecture (sub-systems like Camera/Display/GPU/memory/security modules, etc.) and developing the required test software. Ability and expertise in quickly understanding the sub-system architecture and the corresponding test plans is a must. The job also involves executing this software on emulation hardware and FPGAs in pre-silicon and the actual development board in post-silicon. You will be working with global teams, and this is an excellent opportunity to interact with the best in the world. You should be comfortable with C programming and scripting languages like Python and TCL. Must Have Skills: Deep understanding of PCIe Gen3/Gen4/Gen5 (and emerging Gen6) specifications, including transaction, data link, and physical layers. Proven experience in PCIe protocol-level validation, error injection, and compliance testing. Strong proficiency in C programming for embedded systems. Knowledge of ARM architecture and subsystems. Good to Have: Familiarity with ASIC verification methodologies and proven experience in verification processes. Experience with hardware emulators like Synopsys Zebu, Cadence Palladium, or Mentor Veloce. Knowledge of Pytest, TCL, and Bash scripting. Experience in consumer electronics, particularly in products involving displays and camera peripherals. Understanding of RTL-level verification techniques. Familiarity with FreeRTOS for real-time operating systems. Experience with Linux system programming (threads, mutexes) and ARM booting processes. Non-Technical Skills: Strong analytical and problem-solving skills. Excellent debugging and troubleshooting capabilities. Clear and effective verbal and written communication. Self-motivated with a strong ability to learn and adapt. Eager to take on new challenges and responsibilities.

Bengaluru, Karnataka, India Category: People Hire Type: Employee Job ID 11914 Date posted 07/02/2025 ; We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, powering advancements from self-driving cars to learning machines. As a global leader in chip design, verification, and IP integration, we empower the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation and make a meaningful impact on the world. You Are: A seasoned HR professional with a proven ability to navigate complex organizational challenges and deliver impactful solutions. You are a trusted advisor who provides clear, timely, and accurate HR guidance to employees, managers, and leadership. Your expertise in employment legislation, HR operations, and employee relations enables you to address issues effectively while fostering a positive and inclusive workplace culture. You thrive in high-growth, transformation-driven environments and are skilled at managing escalations, mitigating risks, and driving organizational change. Your analytical mindset allows you to interpret talent metrics, identify trends, and recommend actionable strategies to improve employee retention, performance, and satisfaction. Collaboration is at the core of your approach. You work seamlessly with People Partners, Talent teams, Legal, and Shared Services to implement HR initiatives that align with business objectives. With a strong understanding of HR systems and global team dynamics, you are ready to contribute to Synopsys' success by enhancing operational efficiency and driving business impact. What You’ll Be Doing: Responsible for HR foundational processes, escalations from Shared services team (Tier-3) Ensure risk mitigation, talent management processes, ensuring smooth and effective employee experience Work closely with people partners, talent COEs, shared services and business leaders to drive operational efficient and business impact Ensure to provide clear and accurate HR guidance to employees, managers, and leadership on policies, processes, and best practices. Offer expertise on employment legislation, compliance, and HR operations to support your client groups, while managing a team Investigate recurring issues, identify root causes, and collaborate with People Partners and Centres of Excellence (COEs) to implement long-term solutions. Partner with site leaders and People Partners to drive HR initiatives, including employee engagement actions based on survey feedback. Provide data-driven insights to support decision-making and workforce optimization. Conduct regular reporting and analysis to identify proactive HR actions for retention, performance management, and employee experience improvement. Review and analyse talent metrics to identify trends and recommend solutions that enhance organizational performance. Plan, manage, and continuously improve leadership review processes and strategic objectives. The Impact You Will Have: Enhance HR operational efficiency and consistency across the region, ensuring a seamless employee experience. Support business growth and transformation by implementing strategic HR initiatives that align with organizational goals. Improve employee engagement and satisfaction by addressing and resolving HR issues effectively. Drive data-driven decision-making to optimize workforce performance, retention, and overall employee experience. Ensure compliance with employment laws and HR best practices, minimizing risks and fostering trust. Build a collaborative and high-performance culture that empowers employees and drives organizational success. What You’ll Need: Bachelor’s degree in Human Resources, Business Administration, or a related field (or equivalent work experience). 8+ years of HR experience in high-growth, transformation-driven environments, with a focus on HR operations, employee relations, and business enablement. Strong understanding of employment laws, compliance, and HR best practices. Proven ability to manage HR escalations, labor relations, and organizational change in dynamic business settings. Proficiency in HR systems such as SuccessFactors, ServiceNow, and Visier, with a focus on data-driven decision-making. Experience working with global teams and navigating cross-cultural dynamics. Who You Are: A collaborative and proactive problem-swho can balance short-term needs with long-term goals. Detail-oriented and organized, with the ability to manage multiple priorities effectively. Resilient and adaptable, thriving in a fast-paced and ever-changing environment. A team player who values diversity and fosters an inclusive workplace culture. The Team You’ll Be A Part Of: You will join a high-performing People team dedicated to driving operational excellence and business impact. Collaborating with People Partners, Talent teams, Legal, and Shared Services, you will play a pivotal role in shaping the employee experience and supporting organizational growth. This team is committed to fostering a culture of innovation, collaboration, and continuous improvement. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings, ensuring you feel supported in all aspects of your life. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a robust understanding of project and program management. You have a knack for driving the on-time delivery of patches and releases for small products and can assist with larger product releases. You possess excellent interpersonal and communication skills, enabling you to interface seamlessly between R&D, DevOps, management, and Application Engineers. You bring a wealth of experience in software development, particularly in C/C++, and have an in-depth knowledge of project management concepts. Your passion for customer focus and quality is evident in your work, and you are always on the lookout for tools and automation to improve productivity and quality. You thrive in a process-oriented environment, are confident in handling conflicting situations, and can work effectively across multiple teams and geographies. Your background in the EDA domain and knowledge of configuration management tools and Unix environments make you a valuable asset. With over 8 years of relevant experience in program management, process and releases, or software development, you are ready to take on new challenges and drive success for Synopsys. What You’ll Be Doing: Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. The Impact You Will Have: Ensure timely delivery of product patches and releases, contributing to overall project success. Support the scalability and reliability of Synopsys products through meticulous project management. Foster seamless communication and collaboration among cross-functional teams. Implement innovative ideas to streamline processes and improve product quality. Enhance customer satisfaction through a strong focus on quality and timely delivery. Drive productivity improvements by leveraging tools and automation techniques. What You’ll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities. Who You Are: Process-oriented and confident in handling conflicting situations. Flexible, resourceful, and responsible in completing assigned tasks. Passionate about customer focus and quality. Enthusiastic about trying new tools and automation for productivity and quality improvements. Experienced in multi-team, cross-geography product delivery. The Team You’ll Be A Part Of: Join a dynamic and innovative team focused on driving the success of Synopsys products. Our team is dedicated to delivering high-quality software and hardware solutions through collaborative efforts and cutting-edge technology. You will work alongside talented professionals who are passionate about innovation and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a talented, energetic, and experienced individual with a passion for Linux administration and cloud operations. With a strong foundation in Azure fundamentals, you excel in maintaining high-performance cloud environments. Your ability to communicate effectively, make practical decisions, and deliver agile goals sets you apart. You bring a wealth of experience in customer support, systems administration, and network operations, making you an ideal candidate for our team. You thrive in a dynamic environment, adept at multitasking and problem-solving, and you are ready to take on the challenge of ensuring the smooth operation of Synopsys Cloud. Your hands-on experience with UNIX system administration, coupled with your proficiency in scripting languages like Shell and Python, makes you a critical asset to our operations support team. What You’ll Be Doing: Design, automate, and support Linux systems and services in a 24*7 production environment. Work both independently and collaboratively to evaluate, recommend, and implement technical solutions that meet business needs. Collaborate with other technical teams to solve problems and continually evolve the technology landscape. Troubleshoot issues to identify root causes and help unblock the customer. Prepare and maintain comprehensive documentation of systems, standards, configurations, and procedures. Support day-to-day operations, including installation, configuration, maintenance, and troubleshooting of the engineering secure computing environment. The Impact You Will Have: Ensuring the high performance and reliability of the Synopsys Cloud environment. Contributing to the seamless operation and security compliance of our cloud infrastructure. Enhancing the efficiency and effectiveness of our technical solutions through continuous evaluation and implementation. Collaborating with cross-functional teams to drive innovation and solve complex technical challenges. Providing critical support and troubleshooting to maintain uninterrupted services for our customers. Maintaining up-to-date documentation to ensure consistency and compliance across our systems. What You’ll Need: Extensive knowledge of Linux operating systems and security patching. Experience in installing, monitoring, and administering Linux systems (Ubuntu and RHEL primarily). One or more Linux System Administrator Certifications. Proficiency with monitoring and logging tools. Strong programming/scripting skills in Shell/Python. Who You Are: Proficient in basic networking fundamentals, including TCP/IP, DNS, subnetting, and routing. Knowledgeable in networking for virtual machines, particularly regarding security and performance. Experienced with remote desktop software solutions, such as VNC, Citrix Xen server, and VDI. Solid understanding of infrastructure services like Kickstart, NFS, DNS, and DHCP. Familiar with Azure resources like VM, Network, NSG, and Blob Storage. Able to communicate technical concepts clearly to both technical and nontechnical users. Proven ability to work collaboratively in a dynamic team environment to resolve complex problems. Enthusiastic and capable of learning on the job. The Team You’ll Be A Part Of: Our team is dedicated to building, operating, and maintaining a high-performance Synopsys Cloud environment. We focus on ensuring smooth operations, compliance with security policies, and driving continuous innovation. You will work alongside a group of highly skilled professionals who are passionate about technology and committed to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

Location Karnataka Bengaluru Experience Range 5 - 10 Years Job Description 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it’s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Hyderabad, Telangana, India Category: General Management Hire Type: Employee Job ID 6538 Date posted 07/01/2025 ; We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a robust understanding of project and program management. You have a knack for driving the on-time delivery of patches and releases for small products and can assist with larger product releases. You possess excellent interpersonal and communication skills, enabling you to interface seamlessly between R&D, DevOps, management, and Application Engineers. You bring a wealth of experience in software development, particularly in C/C++, and have an in-depth knowledge of project management concepts. Your passion for customer focus and quality is evident in your work, and you are always on the lookout for tools and automation to improve productivity and quality. You thrive in a process-oriented environment, are confident in handling conflicting situations, and can work effectively across multiple teams and geographies. Your background in the EDA domain and knowledge of configuration management tools and Unix environments make you a valuable asset. With over 8 years of relevant experience in program management, process and releases, or software development, you are ready to take on new challenges and drive success for Synopsys. What You’ll Be Doing: Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. hands-on experience in C/C++ software development to enhance project outcomes. The Impact You Will Have: Ensure timely delivery of product patches and releases, contributing to overall project success. Support the scalability and reliability of Synopsys products through meticulous project management. Foster seamless communication and collaboration among cross-functional teams. Implement innovative ideas to streamline processes and improve product quality. Enhance customer satisfaction through a strong focus on quality and timely delivery. Drive productivity improvements by leveraging tools and automation techniques. What You’ll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities. Who You Are: Process-oriented and confident in handling conflicting situations. Flexible, resourceful, and responsible in completing assigned tasks. Passionate about customer focus and quality. Enthusiastic about trying new tools and automation for productivity and quality improvements. Experienced in multi-team, cross-geography product delivery. The Team You’ll Be A Part Of: Join a dynamic and innovative team focused on driving the success of Synopsys products. Our team is dedicated to delivering high-quality software and hardware solutions through collaborative efforts and cutting-edge technology. You will work alongside talented professionals who are passionate about innovation and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We are looking for passionate and detail-oriented Analog or PCB Layout Design Interns to join design team. This is an excellent opportunity for engineering and diploma candidates to gain experience in real-world circuit design and PCB development. Analog Engineer Intern : Assist in designing analog circuits, including amplifiers, filters, power supplies, etc. Simulate analog circuits using tools such as LTSpice, PSpice, or Multisim. Participate in circuit debugging and validation on breadboards and PCBs. Work with engineers to improve circuit performance and reliability. Document schematics, simulation results, and testing procedures. PCB Layout Design Intern : Assist in schematic capture and PCB layout design using tools like Altium Designer, KiCad, Eagle, or OrCAD. Learn about PCB stack-up, trace width, clearance, and impedance control. Participate in Design Rule Checks (DRC) and Electrical Rule Checks (ERC). Support in preparing Gerber files and other manufacturing documents. Coordinate with hardware and manufacturing teams for PCB assembly and testing.

VLSI Design Engineer Job Title : VLSI Design Engineer Location : Chennai, Hyderabad, Bangalore Experience : 1-4 Overview: Works on the design and verification of integrated circuits (ICs), including ASICs and FPGAs, for high-performance applications. Key Responsibilities: RTL design using Verilog/VHDL. Functional verification and synthesis. Timing analysis and power optimization. Collaborate with layout and physical design teams. Tools & Technologies: Synopsys Design Compiler, Cadence Virtuoso Model Sim, Viva do, Quartus Verilog, VHDL Career Path: VLSI Lead Chip Design Architect Semiconductor R&D Manager

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Looking for a high-performance individual to work on the Synopsys next generation emulation solutions encompassing Virtual and Physical interface solutions on for PCIE, CXL, USB, Ethernet. The selected candidate will work on product verification and product engineering of these products ensuring all system level scenarios in the concerned product/solution are exhaustively verified and gets deployed at hyperscale customers. The person is required to be motivated and self-driven and would work among a knowledgeable and experienced set of people, adding to his/her learning. Academic Qualification/Skills required: B.E / M.E. in Electronic & Communication / Computer Science Engineering High performance individual to work on Synopsys next generation emulation solutions for PCIe, USB, Ethernet protocols Good knowledge of one of peripheral protocols primarily PCIe, USB, Ethernet Knowledge of System Level verification and validation, and digital design concepts Knowledge of languages such as Verilog, System Verilog, C/C++, and scripting languages- Perl/TCL/Shell, Python Knowledge of emulation and prototyping domains an added advantage 6-8 Years of experience in protocols/design verification and validation, scripting, and automation Good communication skills and team player

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background in custom design and Standard Cell Design methodologies. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What You’ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art circuit components for SLM monitors realized through ASIC design flow. Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. Developing statistical simulation methodologies and collaborating with the layout team to achieve optimal design solutions. Characterizing designed custom cells and deploying new circuits into test chips for post-silicon characterization. Creating new cells and updating existing ones through collaboration with architects and Physical Design engineers. Conducting pre and post-layout simulations and characterizations across various design corners to ensure reliability and aging requirements. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. Enhancing the reliability and differentiation of products in the market with reduced risk. Driving innovation in custom circuit design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience. Strong custom design experience, including specification, circuit design description, and schematics. Proficiency with circuit design and simulation tools, IC design CAD packages from any EDA vendor. Sound understanding of SPICE simulator concepts and simulation methods. Experience with statistical design methodologies like generating and analyzing Monte-Carlo results. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing circuit solutions. Excellent communicator and team player, capable of collaborating effectively with diverse teams. Innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You’ll Be A Part Of: You will be part of the SLM Monitors group, a team dedicated to building next-generation intelligent in-chip sensors, hardware/software capabilities, and analytics. Our team focuses on developing and integrating solutions that manage and improve each semiconductor lifecycle stage, enabling customers to bring differentiated products to market quickly with reduced risk. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys is seeking a software specialist with strong experience in user interface development for the QuantumATK atomic-scale simulation platform You must have a background in scientific computing and several years’ experience building complex and powerful user interfaces for scientific applications. Ideally this includes experience with full-stack web development, UI frameworks like React or Vue, and web backend development and server-client based applications. We are looking for outstanding individual that: Has at least a master’s in science, computer science or related fields and strong general background in solid state physics or chemistry Has proven experience developing user interfaces for scientific software applications. Has a strong scientific background with clear relevance to atomic scale modelling. Proven experience with development of complex and powerful user interfaces for scientific applications. Requirements : Excellent programming skills, and broad programming experience. Primarily Python and C++ but for this role it is an advantage to have experience with web technologies. Proven interest in layouting, visual design and UI programming 6+ years of industry experience in similar domain Great written and oral communication skills in English.

JOB DESCRIPTION As FPGA Architect , you will lead the design & development effort on a variety of projects in a highly collaborative, fast-paced environment. In this role, you will be responsible for the definition and development of complex FPGA designs for our Test products. You will work closely with R&D Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US & Europe. Qualifications Essential: Bachelor degree or Master's degree in electrical / Electronic Engineering Minimum 10 years of R&D experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Experience of Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. Experience of EDA Functional Simulation tools – Synopsys or Mentor or Cadence Experience of Altera or Xilinx FPGA Tools Design Flow Ability to quickly learn new technologies, protocols and product segments Experience of creating self-checking Simulation environment involving test bench, scripts for automation, writing test cases. Collaborate with system architects to define the system architecture and determine how the FPGA will interface with other components on the PCA board and choose an appropriate FPGA based on the project's requirements. Experience with timing closure for complex designs Excellent written skills which are required for creating documents like Product Definition, Detailed FPGA Design, Hardware & Software Interface documents Self-motivated and self-organized Excellent team-player, responsive and accountable Excellent verbal communication skills Preferred: Experience with Keysight instruments like Oscilloscope, Analyzer, AWG & BERT Experience of working on Protocols such as PCI Express, USB, MIPI (MPHY, DPHY, CPHY based), Ethernet, DDR etc. Experience in international collaboration (US & EUR) Experience in multi-vendor collaboration (software supplied by and/or to external organizations) Job Type: Full-time Pay: ₹2,000,000.00 - ₹2,500,000.00 per month Benefits: Flexible schedule Work Location: In person

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Grow with us About this opportunity: We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 768638

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a passion for innovation and a drive for excellence. You possess a strong background in digital design and verification, with a keen understanding of microprocessor architectures. Your technical expertise and analytical skills enable you to develop and maintain complex hardware-software co-simulation environments, create functional and code coverage models, and manage regression testing effectively. You thrive in a collaborative, multi-cultural, and multi-time zone team environment, and your excellent communication skills allow you to work seamlessly with colleagues and stakeholders. Your experience with HDL and verification languages such as System Verilog and Verilog, along with your proficiency in programming languages like C, C++, assembly, Python, and Perl, make you an invaluable asset to the team. You are adept at using RTL simulators and other verification tools, and you are always eager to learn and adapt to new technologies and methodologies. What You’ll Be Doing: The candidate will be a key member of the Synopsys DesignWare ARC Processor hardware team working on next-generation ARC processor Verification. Responsibility includes development of Processor Testbenches and automation, functional coverage model creation and report analysis, code coverage analysis, integration of third party and internal verification IP, regression management. Candidate is expected to work with multi-site, multi-time zone, multi-cultural teams on various aspects ARC processor verification. Creating and automating testbenches for verification processes. Creating functional coverage models and analyzing reports. Performing code coverage analysis to ensure thorough verification. Integrating third-party and internal verification IPs. Managing regression testing and ensuring test coverage. The Impact You Will Have: Ensuring the reliability and performance of next-generation ARC-V processors. Contributing to the development of cutting-edge silicon IP solutions. Enhancing the efficiency and effectiveness of verification processes. Reducing time-to-market for high-performance, low-risk products. Collaborating with global teams to drive innovation and excellence. Helping Synopsys maintain its leadership in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering (required). 4+ years of related experience in digital design and verification. Strong knowledge of digital design principles. Experience with microprocessor architectures (a plus). Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Experience with RTL simulators and verification tools. Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural environment. Analytically minded with exceptional problem-solving skills. Detail-oriented and committed to delivering high-quality work. Adaptable and eager to learn new technologies and methodologies. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people It requires a consistent and committed practice, something we call the Juniper Way ASIC Engineer Staff Physical Design Experience: 9+ Years Location: Bangalore Job Specification Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs The position requires good understanding of the physical design flow from RTL to GDS & several chips tapeout experience The successful candidate should possess in-depth knowledge & experience in physicalsynthesis, design planning, floor planning, place & route, static timing analysis and designclosure & physical verification Responsibilities Will be responsible to lead/implement multiple blocks, may need to mentor or lead a small group of engineers, track their block convergence, effectively communicate with Fullchip or front end teams actively for the smooth closure of blocks Should be capable of handling critical blocks closure in fire fighting situations Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow Experienced in design automation Understanding of Timing constraints, SI prevention, Power reduction Must have prior experience with Synopsys/Cadence/Mentor place and route tools Must have completed design in 16nm and or 7nm Proficient in Unix/TCL/Perl Good communication and presentation skills Requires good interpersonal skills and problem-solving ability Minimum Qualifications 9+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era We do this with products, solutions and services that transform the way people connect, work and live We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world Additional information can be found at Juniper Networks (www juniper net) or connect with Juniper on Twitter, LinkedIn and Facebook WHERE WILL YOU DO YOUR BEST WORK Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking where colleague innovation is not only valued, but expected We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work At Juniper we believe this is more than a job it's an opportunity to help change the world At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together If you think you have what it takes, but do not necessarily check every single box, please consider applying Wed love to speak with you Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire Juniper Networks participates in the E-Verify program E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers Information for applicants about E-Verify / E-Verify Informaci?n en espa?ol: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) The Right to Work / El Derecho a Trabajar E-Verifyis a registered trademark of the U S Department of Homeland Security Juniper is an Equal Opportunity workplace We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic All employment decisions are made on the basis of individual qualifications, merit, and business need

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation . Must have hands-on experience on Synopsys/Cadence tools. Should have experience on PD Methodologies and submicron technology of 28nm and lower technology nodes.