Senior Analog Layout Design Lead

As a Senior Analog Layout Design Engineer / Lead at Eximietas Design, your role will involve optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You are expected to have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. Your responsibilities include understanding how layout impacts circuit performance, implementing high-quality layouts meeting tight design constraints, and collaborating with cross-functional teams. Key Responsibilities: - Optimize IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. - Understand and mitigate the impact of layout on circuit performance. - Implement layouts meeting tight design constraints and ensuring high quality. - Utilize CADENCE/SYNOPSYS layout tools and flows effectively. - Utilize scripting languages (PERL/SKILL) for enhanced efficiency. - Collaborate effectively with cross-functional teams. Qualifications Required: - 7-15 years of experience in analog layout design. - Expertise in lower FINFET technology nodes, particularly TSMC 5nm. - Strong communication skills and experience collaborating with cross-functional teams. If you are passionate about pushing the boundaries of analog layout design and possess the required expertise, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. Eximietas Design is excited to connect with talented engineers like you who are dedicated to advancing analog layout design.,