6 Rc Delay Jobs

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability to meet tight design constraints, and deliver high-quality layouts. The ideal candidate will have hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages such as PERL/SKILL is a plus. Additionally, strong communication skills and experience collaborating with cross-functional teams are essential for success in this role. If you are interested in this opportunity or know someone who would be a great fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to hearing from you! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL is a plus. Strong communication skills are necessary as you will be working with cross-functional teams. If you are interested in this opportunity or know someone who would be suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Requirements: - Proficiency in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Strong comprehension of how layout impacts circuit performance metrics such as speed and area. - Ability to create layouts that meet rigorous design constraints and uphold quality standards. - Hands-on experience with CADENCE/SYNOPSYS layout tools and workflows. - Familiarity with scripting languages such as PERL/SKILL is considered a plus. - Excellent communication skills with a proven track record of collaborating effectively with cross-functional teams. If this opportunity aligns with your expertise and interests, or if you know someone who would be a suitable fit, please forward your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Best regards, Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Email: maruthiprasad.e@eximietas.design Phone: +91 8088969910,

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts that meet tight design constraints. Key Skills & Requirements: - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Solid understanding of how layout impacts circuit performance. - Ability to implement layouts meeting tight design constraints and delivering high quality. - Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. - Familiarity with scripting languages (PERL/SKILL) is a plus. - Strong communication skills and experience collaborating with cross-functional teams. If you find this opportunity intriguing or know someone who would be a good fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Contact: +91 8088969910.,

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross-functional teams are also key to success in this role. If you are interested in this opportunity or know someone suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are looking forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design. Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

You are invited to join Eximietas Design as a Senior Analog Layout Design Engineer/Lead with 7-15 years of experience. We are a rapidly growing team seeking professionals skilled in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. Your key responsibilities will include expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You must be able to implement layouts that meet strict design constraints while ensuring high quality. Proficiency in CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL would be advantageous. Strong communication skills are necessary as you will collaborate with cross-functional teams. If you are interested in this exciting opportunity or know someone who might be a suitable fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated, and we are eager to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to welcoming you to our dynamic team at Eximietas Design.,