12 Rc Delay Jobs

Hiring: Senior Analog Layout Design Leads & Architects Location: Bengaluru/Visakhapatnam Experience: 10+ Years Company: Eximietas Design...! Greetings from Eximietas Design! We are looking for an experienced Senior Analog Layout Design Leads & Architects to join our team in the Bengaluru/Visakhapatnam Location. Required Technical Expertise: We're looking for highly skilled professionals with strong expertise in lower FINFET technology nodes to contribute to cutting-edge analog layout development. Key Skills & Requirements: Deep knowledge of IR drop , Electromigration , self-heating , RC delay , and parasitic capacitance optimization Strong understanding of layout impact on circuit performanc...

As a Senior Analog Layout Design Lead or Architect at Eximietas Design, you will have the opportunity to contribute to cutting-edge analog layout development using advanced lower FINFET technology nodes. Your role will involve deep knowledge of IR drop, Electromigration, Self-heating, RC delay, and Parasitic capacitance optimization. You will be responsible for understanding the layout impact on circuit performance, delivering high-quality layouts under tight design constraints, and utilizing Cadence/Synopsys layout tools and flows. Familiarity with PERL / SKILL scripting would be an added advantage. Strong communication skills and experience collaborating with cross-functional engineering t...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be part of a rapidly growing team specializing in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Solid understanding of how layout impacts circuit performance, such as speed and area - Ability to implement layouts that meet strict design constraints while ensuring high quality - Proficiency in CADENCE/SYNOPSYS layout tools and flows - Familiarity with scripting languages like PERL/SKILL would be advantageous - Strong communicat...

Role Overview: As an Analog Layout Engineer at Eximietas, you will be responsible for critical analog layout design of various blocks such as LDOs, DC-DC converters, ADC/DACs, PLLs, Oscillators, Temperature sensors, Bandgap references, voltage monitors, Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE. Key Responsibilities: - Hands-on experience in critical analog layout design - Understanding and managing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Knowledge of layout effects on circuit performance such as speed and area - Implementing high-quality layouts based on design constraints - Collaboration with cross-functional teams - P...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross...

As a Senior Analog Layout Design Engineer / Lead at Eximietas Design, your role will involve optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You are expected to have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. Your responsibilities include understanding how layout impacts circuit performance, implementing high-quality layouts meeting tight design constraints, and collaborating with cross-functional teams. Key Responsibilities: - Optimize IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. - Understand and mitigate the im...

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability t...

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design cons...

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Re...

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts th...

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area...

You are invited to join Eximietas Design as a Senior Analog Layout Design Engineer/Lead with 7-15 years of experience. We are a rapidly growing team seeking professionals skilled in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. Your key responsibilities will include expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You must be able to implement layouts that meet strict design constraints while ensuring high quality. Proficiency in CADENCE/SYNOPSYS layou...