SOC Physical Design Engineer Lead

Intel

8 - 12 years

17 - 22 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

physical design soc design verification lvs drc synthesis static timing analysis power system process technology rtl distribution design engineering cadence estimation electricals node floor planning dft timing closure synopsys structural design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

B.Tech. or M.Tech. in Electrical/Electronics Engineering with 8-12+ years' of experience.
Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
Experience in timing signoff, formal verification and low power static signoff.
Experience in all aspects of clock distribution.
Experience in deep submicron process technology nodes is strongly preferred.
Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

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