SMTS Software Engineer

AMD is looking for a talented, self-driven and motivated engineer to technically lead AIG s Simulation Modeling projects working on AMD s XDNA (AI Engine) architecture and the Vitis AI family of software tools. The XDNA is an industry leading architecture in terms of performance per watt and is used in AMD s client and embedded devices as the primary engine for Machine Learning workloads. It is the hardware engine behind Windows Co-pilot on AMD devices. The team provides a fast-paced environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated technical issues to resolution. They should have demonstrated ability to identify technical problems, explore and propose viable options, and apply technical solutions. They should be able to excel in a global team environment with strong verbal and written communication skills. . KEY RESPONSIBILITIES: Vitis AI is AMD s primary SDK that enables users to compile and run their ML models on the XDNA architecture. As a senior member of this high-performance team, the selected candidate will have responsibility to model the XDNA architecture in terms of functionality, accuracy and simulation speed. Candidate will work with compiler, runtime/driver teams to bring up latest AI models like CNNs, Transformers, StableDiffiusion, NLPs etc. on the XDNA simulator. This is a crucial part of AMD s shift-left strategy for the successful bring up of new devices and day 0 enablement of models. Candidates would develop a deeper understanding of the various ML models, and how they are executed, identify performance bottlenecks and enable faster development. PREFERRED EXPERIENCE: Minimum 10 years of relevant work experience. Strong background in C++ based development and debug, dealing with multi-threaded infrastructure and performance optimization Experience in creating cycle accurate modeling of IPs in C++ or SystemC / TLM. Understanding of SoCs, and bringing up of software stack from driver to application on simulation model. Understanding hardware metrics like latency/throughput on any sub-system, and what changes impact those metrics. Experience in software development environment on both Linux and Windows is required. Experience in technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired. ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent