82 Silicon Validation Jobs - Page 2

Job Summary We are looking for highly skilled and efficient engineer to join our System Power, Thermal and Performance team. The candidate will have hands-on experience in executing CPU, GPU, and AI/ML workloads on Android and Windows platforms, o with a strong understanding of SoC subsystems and performance/power KPIs. This role involves system validation, power and performance measurements and optimization, automation, data analysis and handling lab equipment Key Responsibilities Execute and analyze CPU/GPU/AI-ML workloads and benchmarks on Android and Windows platforms Run and interpret power, thermal and performance KPIs from CPU/GPU synthetic workloads and system benchmarks. Execute and collect power and performance KPIs from MLPerf, GenAI models, Vision workloads Collect logs and profiling data from different SoC subsystems (CPU, NPU, DDR, etc.). Monitor and evaluate power and performance KPIs for dashboard generation and reporting. Develop and maintain automation scripts using Python, Shell, or Batch for data collection, parsing, and report generation. Operate lab equipment such as oscilloscopes, power analyzers, and other tools.

We are seeking a skilled and proactive Senior Lead Engineer to drive silicon validation activities for our next-generation semiconductor products. The role involves leading validation strategy, planning, execution, and debug at both pre-silicon and post-silicon phases. Key Responsibilities: Define and lead silicon validation plans, schedules, and resource allocation. Develop and execute test methodologies for functional, performance, and reliability validation. Collaborate with design, verification, and systems teams to ensure coverage of all validation requirements. Lead bring-up and debug of silicon in the lab environment using oscilloscopes, logic analyzers, and other equipment. Analyze test results, identify issues, and drive root-cause resolution with cross-functional teams. Provide technical guidance and mentorship to junior validation engineers. Qualifications : Bachelor or Master degree in Electronics Engineering or related field. 812 years of experience in silicon validation or hardware testing. Strong expertise in lab instrumentation, validation methodologies, and debugging complex SoCs. Experience with scripting (Python, Perl) and automation frameworks is desirable. Excellent communication and leadership skills.

Individual Contributor role for Technical leader with 10+ years of experience in Analog and Power IC development within 2. 6B$ Power Business Unit at Renesas. Primary responsibilities include leading the design and development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas s massive Power product portfolio. In the Technical leader role, candidate will be directly responsible for end-to-end IC design (from specifications to PRA). Will be expected to work with other team members to do successful Chips along with mentoring the junior members. This is an IC role with complete focus on product development and no people management. Essential Functions: Must have led and should be experienced of developing multiple Power ICs with Switching Converters, starting from system level specifications and taking ICs to production. Identify and resolve technical challenges and risks. Provide technical expertise and mentorship to junior engineers. Able to lead group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs. Must be proficient in designing complete switching converters and all involved I/Ps. Should be fully aware of all challenges pertaining to high current/power switching converters design including Noise, Power dissipation etc and their mitigation. Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability. Should be able to lead and guide development, integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must. Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. Should be able to architect the IC and break down System/Chip-top level requirements into block level specifications and then work with Team members and develop the blocks, integrate the blocks into Top level and ensure desired performance. Must have good understanding of commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each. Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance. Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance. Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges. Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy. Should have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC Minimum Requirements: Bachelor s or master s degree in electrical engineering 10+ years in Analog Circuit Design. Solid understanding and design experience of complex analog designs with full ownership. Chip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production. Must be a technical leader & natural team player, mentor and should strive towards fostering a highly creative and productive working environment

Job Summary We are seeking a Principal Post-Silicon Validation Engineer to lead the system-level validation, debug, and bring-up of complex SoCs for cutting-edge AI, HPC, automotive, MCU and data center products. In this senior role, you will drive post-silicon validation strategy , coordinate across hardware and software teams, and ensure the delivery of high-quality, production-ready silicon . Experience with Virtual Modeling, SystemC, and TLM is a plus , supporting pre-silicon co-validation and accelerating silicon bring-up. Key Responsibilities Post-Silicon Validation Planning & Execution Define and lead comprehensive post-silicon validation plans , including functional validation, performance tuning, stress testing, and interoperability . Develop and execute system-level test content , leveraging real-world workloads, benchmarks, and custom test suites. Drive silicon bring-up , working closely with cross-functional teams to ensure first-pass success. Silicon Debug & Issue Resolution Lead complex issue triage, debug, and root cause analysis using hardware debug tools (logic analyzers, protocol analyzers, JTAG, trace). Interface with design, verification, and firmware teams to resolve issues found in silicon and drive corrective actions. Collaboration & Cross-Functional Coordination Work closely with design, verification, firmware, software, and system teams to align validation goals and schedules. Provide critical feedback to architecture and design teams on silicon behavior and feature readiness. Validation Infrastructure Development Develop and enhance validation frameworks, automation scripts, and post-silicon diagnostics to accelerate validation cycles. Contribute to lab infrastructure setup , including platform bring-up, test environments, and debug tool integration. Leadership & Mentorship Lead technical reviews, debug task forces, and post-silicon readiness assessments . Mentor junior engineers and drive a culture of technical rigor and innovation . Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in post-silicon validation, hardware bring-up, or related SoC/system validation roles. Technical Expertise Proven track record of silicon bring-up and validation for complex SoCs or silicon systems. Strong understanding of SoC architecture, high-speed interfaces (PCIe Gen5/6, CXL, DDR5, HBM3) , and embedded system design. Hands-on expertise in system-level validation , performance tuning, and debug of complex SoC designs. Debug & Validation Tools Proficient in hardware debug tools (JTAG, logic analyzers, protocol analyzers), as well as embedded software and firmware-level debugging. Experience with diagnostic software and post-silicon validation frameworks . Soft Skills Excellent problem-solving and analytical skills , with a methodical approach to debug and issue resolution. Strong communication and collaboration skills to work across multi-disciplinary teams.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Core Switch Group (CSG) at Broadcom is the industry leader in cutting-edge networking ASICs, developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team is behind iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazines "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If youre a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium . Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring Bachelor s with 12+ years in emulation or post-silicon validation of networking ASICs. Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. Excellent communicator who thrives in a collaborative, fast-paced environment.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Core Switch Group (CSG) at Broadcom is the industry leader in cutting-edge networking ASICs, developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team is behind iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazines "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If youre a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium . Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring Bachelor s with 12+ years in emulation or post-silicon validation of networking ASICs. Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. Excellent communicator who thrives in a collaborative, fast-paced environment. .

Minimum qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 3 years of experience in software development in the area of consumer electronics or other embedded systems. 2 years of experience driving application-specific integrated circuit (ASIC) architecture , OS kernel, system on a chip (SoC) architecture, power and performance analysis. Preferred qualifications: Master's degree or PhD in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 5 years of experience in software design and development for software layers found in SoC (e.g., bootloaders, kernel, hypervisor, secure monitor, device drivers and embedded firmware). Experience with Android and any Real-time OS. Knowledge of interaction types between hardware and software for different types of standard hardware blocks, CPU, and accelerators. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Silicon Software team has the long term charter to develop software for a variety of custom silicon being developed within Google. This includes IP for many diverse applications. We are working generations ahead of the market to enable groundbreaking features. In this role, you will be involved in developing software across a few domains such as platform software (BSP, firmware, drivers) delivered to our customers, silicon validation software to be used in the pre-silicon, and post-silicon validation, compilers, drivers, runtime, embedded firmware and tools in the machine learning domain, security architecture and systems, system power and performance, related engineering productivity and test engineering activities.Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Collaborate with stakeholders to identify user experiences characteristics and how they can be mapped onto hardware and software. Design architecture and software interfaces that enable application developers to make use of hardware accelerators and other IP. Understand interactions between hardware components, identify issues and bottlenecks, provide trade-off options and drive them to resolution. Help design or improve hardware from generation to generation based on lessons learned from productization efforts, and to reduce technical debt.

Minimum qualifications: Bachelor degree in Computer Science, Electrical Engineering or equivalent practical experience. Experience with coding such as C or Python. Experience with Computer Architecture and Memory Organization Preferred qualifications: Master's degree in Computer Science, Electrical Engineering or equivalent practical experience. Experience in Developing test and debug infrastructure such as software tools, lab equipment and test/lab automation scripting. Experience with using Prototyping platforms like Emulators or FPGAs. Experience with power or performance measurement of SoCs. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work with Architecture, Design and product teams to understand requirements for fabric and cache controller. Understand the design and develop or execute validation tests. Drive the post silicon bring-up and validation activities. Develop various post silicon validation or debug tools.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR). Experience in silicon bringup, functional validation, characterizing, and qualification. Experience with board schematics, layout, and debug methodologies with using lab equipment. Preferred qualifications: Experience in hardware emulation with hardware/software integration. Experience in coding (e.g., Python) for automation development. Experience in Register-Transfer Level (RTL) design, verification or emulation. Knowledge of SoC architecture including boot flows. Knowledge of HBM/DDR standards. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be responsible for post-silicon validation of the Cloud Tensor Processing Unit (TPU) projects. You will create test plans and test content for exercising the various subsystems in the Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoC), verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver high-quality designs for next generation data center accelerators.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production. Ensure validation provides necessary functional coverage for skilled design. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for an SoC Emulation Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. As an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. In this role, you will: Develop/review subsystem testplans and help create the SoC Verification and Validation plan. Implement tests and scenarios on multiple platforms. Develop and deploy baremetal drivers to configure SoC subsystems Pre-silicon activities: Develop test benches, transactors and monitors to work with Emulation systems (ex. Zebu) and Prototyping systems (ex. HAPs) Develop infrastructure for build and runtime of SoC emulation and prototyping models using vendor tools and Providing training, failure debug support and improving debug capabilities Maximize efficient utilization of the platforms through automation and other innovations Debug and resolve issues, pioneer and deploy new platform capabilities Post-silicon activities: Continue pre-silicon efforts to seamlessly intersect and bring up early silicon Port emulation and prototyping testplans to post-silicon activities Write tests and infrastructure to ensure Performant and Functional compliance of Silicon Basic qualifications Bachelor s degree or higher in EE, CE, or CS 5+ years or more of SoC verification or validation experience 2+ years of emulation or prototyping experience utilizing emulators including Palladium, Zebu, and Veloce. Scripting experience with Perl, Python, tcl, shell and drive to automate flows Expertise in C/C++ Excellent communication (oral and written) and analytical skills. Should be able to work closely with design and software teams across multiple sites. Preferred qualifications Have in depth knowledge of entire SoC verification and validation processes Experience bringing up early silicon on reference or test boards As an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. Bachelor s degree or higher in EE, CE, or CS 3+ years experience in pre-silicon verification using SystemVerilog/UVM 3+ years experience in post-silicon validation Very strong problem solving, debug and analysis, and automation skills Experience with verification and validation of complex SOCs Solid grasp of concepts of HW/SW interface Strong programming skills (assembly, C, Perl/Python) Firsthand experience with silicon bringup, complex system debug, or bare-metal programming. Experience in a full development cycle from pre-silicon verification to silicon bringup MS or PhD in Computer Science, Electrical Engineering or related field Experience with ARM and various DSP ISA Experience with SOC fabrics, memory controllers, and SOC peripherals Experience with machine learning, computer vision or robotics Excellence in technical communication with peers and non-technical cohorts Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit https: / / www.amazon.jobs / en / disability / us.

Verification Engineer Location: Bengaluru Experience: 4-8 years Primary Skills 1. Knowledge of one or more Protocols: PCIe, LPDDR, SPI, USB, AXI. 2. Knowledge of ARM and/or x86 SoC Architecture. 3. Strong experience in C programming language, Assembly Language & Python programming. 4. Strong experience in one or more scripting languages Perl/ Python/ TCL etc. 5. Debugging experience. 6. Debugger interface knowledge (Coresight/ UltraSoC, Lauterbach, JTAG). 7. Experience on any emulation platforms (Palladium, Zebu or equivalent). 8. Experience in testing embedded software on SoC, including understanding of HW architecture, board schematics, protocols & standards. 9. Working proficiency and communication skills in verbal and written English. Good to have Skills 1. Experience in coding / development in C, Python. 2. Experience of Palladium compilation/ build flows is a big plus. 3. Power controller chips Knowledge & Testing is a big plus. Qualifications 1. BE degree in Electronics, Computer Science or similar technical field of study or equivalent practical experience. 2. 4 - 8 years of experience in hardware or embedded test and automation role. Responsibilities 1. Pre Silicon Validation / Emulation Engineer responsible for test plan development, test scenario creation and validation of IPs/ SoCs on Palladium emulation platform. 2. Triage, analyze and send comprehensive test results for nightly/ weekly/ Stability test. 3. Automate tests using existing test frameworks and work closely with Test Leads to improve test framework robustness and efficiency.

PMTS SILICON DESIGN ENGINEER Person: As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. We are seeking a highly experienced and motivated DFT (Design for Testability) Lead to join our dynamic team, with a strong background in implementing and managing DFT methodologies. The DFT Lead will be responsible for leading a team of engineers to develop and execute DFT strategies that ensure the highest level of product quality and reliability. Responsibilities Lead the design and implementation of advanced DFT architectures and methodologies. Collaborate with cross-functional teams including design, verification, and manufacturing to ensure seamless integration of DFT features. Develop and optimize test plans for various stages of silicon validation. Drive the adoption of state-of-the-art DFT tools and techniques to improve test coverage and efficiency. Provide technical guidance and mentorship to junior DFT engineers. Analyze test data to identify and resolve issues in a timely manner. Ensure compliance with industry standards and best practices for DFT. Stay updated with the latest advancements in DFT technology and integrate relevant innovations into current projects. Qualifications Extensive knowledge of DFT techniques including scan insertion, BIST, JTAG, and boundary scan. Proficiency in DFT tools such as Mentor Graphics Tessent, Synopsys DFTMAX, and Cadence Encounter Test. Strong understanding of DFX design and verification processes. Excellent problem-solving and analytical skills. Exceptional leadership and team management abilities. Effective communication skills, both written and verbal. ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred with 15+Yrs of exp #LI-SR4

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Principal Engineer, DV We are seeking a highly motivated and experienced Principal SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities - Formal Verification Strategy: Define and implement formal verification methodologies for pre-silicon validation. - Tool Ownership: Master industry tools (e.g., Cadence JasperGold, Synopsys VC Formal) to prove correctness of RTL designs. - Constraint Development: Create assertions (SVA), assumptions, and cover points to model design behavior. - Debugging: Root-cause formal failures and collaborate with RTL teams to resolve design flaws. - Cross-Team Collaboration: Work with architects, designers, and DV teams to align formal efforts with simulation/emulation. - 10+ years of experience required. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Lattice Semiconductor is seeking a Design Engineer-2 FPGA Architecture to join the Architecture team focused on FPGA architecture modeling and advance system architecture. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in architecture modeling and evaluation of Lattice FPGA s and Software tools to measure performance, power, and area for various workloads The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with Software tools team to define benchmarks, measure performance and suggest improvement areas Serve as a technical expert, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and open-minded student Accountabilities: Serve as a key contributor to build FPGA architecture modeling and evaluation platform efforts Drive logic design of key FPGA workloads and bring best-in-class methodologies to accelerate design and test time and quality. Develop the regression testing framework to execute, measure and report architecture modeling and evaluation experiments Ensuring design quality throughout project development conducting regular reviews and audits Perform architecture evaluation of competitive products Work with cross functional team including program management, Software Tools, HW architects, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up to date with the latest industry trends and technologies Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 3+ years of experience in driving logic design across a multitude of FPGA projects. Expertise in FPGA designs, use-cases, and design considerations, defining micro-architecture and experience of working with various EDA tools Experience in leading the project throughout design cycle and working with cross organization Proven ability to work with multiple groups across different sites and time zones. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones.

Tessolve Semiconductor Pvt. Ltd. is looking for Post Silicon Validation Engineer 2 to join our dynamic team and embark on a rewarding career journey Collaborate with cross-functional teams to achieve strategic outcomes Apply subject expertise to support operations, planning, and decision-making Utilize tools, analytics, or platforms relevant to the job domain Ensure compliance with policies while improving efficiency and outcomes

Hi all, We are hiring for the role ASIC Engineer HSIO Post-Silicon Electrical Validation Experience: 3 - 5 Years Location: Hyderabad Notice Period: Immediate - 15 Days Skills: We are seeking a skilled ASIC Engineer to join our High-Speed I/O (HSIO) Post-Silicon Electrical Validation team. The ideal candidate will possess hands-on experience with high-end lab equipment, proficiency in automation scripting, and a solid understanding of high-speed interfaces. This role involves validating and characterizing ASICs post-fabrication to ensure they meet performance, power, and reliability specifications Key Responsibilities Develop and execute detailed post-silicon validation plans for new ASICs. Design and implement test cases in Python, C++, LabView, or VBA for validating functionality, performance, and power metrics. Bring-up silicon in the lab and debug/resolve issues using high-end lab equipment such as oscilloscopes, JBERTs, and power supplies. Analyze and root-cause silicon failures, collaborating closely with design teams to drive resolution. Document validation results, prepare comprehensive reports, and communicate findings effectively to cross-functional teams. Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 35 years of experience in post-silicon validation, hardware bring-up, or related fields. Proficiency in scripting languages such as Python, C++, LabView, or VBA for automation purposes. Hands-on experience with high-end lab equipment, including oscilloscopes, JBERTs, and power supplies. Strong understanding of high-speed interfaces like PCIe, DDR, and USB. Excellent analytical and problem-solving skills. Effective communication skills and the ability to work collaboratively in a team environment. If you are interested drop your resume at saraswati.g@acesoftlabs.com

Overview Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. Responsibilities Strong knowledge of the Basic electronics and Hands on experience with Test & measurement instruments. Solid understanding of protocols like PCIE,DDR,USB and the ethernet technologies.Knowledge on Oscilloscope,BERT and optics.Knowledge on keysight products such as UXR,DSO9000 series scope and M8020A BERT s is added advantage. Strong organisational skills, ability to multi-task, prioritise and work well under pressure. Qualifications Bachelor and/or Master s degree in electronics & communications Technologies or science discipline. A strong level of English language required. Typically, 3-8 years relevant experience woring in Silicon validation,Test & measurement industry. Careers Privacy StatementKeysight is an Equal Opportunity Employer. Strong knowledge of the Basic electronics and Hands on experience with Test & measurement instruments. Solid understanding of protocols like PCIE,DDR,USB and the ethernet technologies.Knowledge on Oscilloscope,BERT and optics.Knowledge on keysight products such as UXR,DSO9000 series scope and M8020A BERT s is added advantage. Strong organisational skills, ability to multi-task, prioritise and work well under pressure.

NVIDIA needs a Senior Custom SOC/IP Verification Engineer for next-gen solutions. Seeking hard-working individuals to build life-changing custom SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: Lead ASIC design verification for various processing blocks in a SOC, including planning, execution, Coverage and methodology development. Collaborate with multiple teams (Architecture, SW/FW, Design, Modeling, Emulation, Post-Silicon Validation) to ensure comprehensive verification plans. Support engineering teams in delivering solutions for purpose-built ASICs and collaborate with IP development teams for IP identification, selection, and licensing. Analyze SOC and IP architecture, develop verification plans, and establish performance metrics. Work with partners in a co-development environment during development, debug, and bringup. Plan tests, achieve coverage closure, and enable customer TB infrastructure. Validate use cases for power-on and boot requirements. What We Need To See: Proficient in design verification tools like Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal. Consistent track record of first-pass success in ASIC Development. Holds a B. S. or M. S. degree in Computer Engineering or Electrical Engineering, with 7+ years of experience in ASIC, IP, or SoC design verification. Skilled in handling mixed language UVM and C++ testbenches, interpreting functional specs, and building comprehensive test plans. Experienced in developing tools and infrastructure using Perl or Python, with a strong background in AMBA protocols (AXI, ACE, CHI, ATB). Hands-on experience with subsystems in new technologies like ARM CPU, LPDDR, HBM, GPUs, DLA, PCIe, and Network on chip, including performance verification. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our Security Subsystem Design deployed in Automotive, GPU, DPU and Client chips. As one of the primary designers, you will be responsible for Security cluster of next generation chips. One should possess strong digital design and verification fundamentals. What youll be doing: As a senior designer, be responsible for understanding system security concepts and features, make architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. During the course of a project you would end up driving the following aspects of design for your unit: Own micro-architecture and RTL development of design modules Micro-architect features to meet performance, power and area requirements Work with HW architects to define critical features Partner with verification teams to verify the correctness of implemented features Work with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. What we need to see: You should be BTech/MTech having a proven track record in crafting complex Units and CPU/micro-controller based Sub-systems 2 + years of design experience Knowledge of security standards, protocols and system security architectures of modern SOCs would be a significant plus Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams Good debugging, analytical and problem solving skills Great interpersonal skills and ability to work as an excellent teammate We have some of the most brilliant and talented people in the world working for us. If youre creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Key Skills : Silicon Validation SoC bring-up Firmware Development SD/MMC Interface System Debugging Job Description : We are hiring for a Senior Engineer Silicon Validation (SD/MMC) to join our hardware validation team. Responsibilities : Collaborate with design and architecture teams to define silicon validation requirements and strategies Develop and maintain firmware for SoC bring-up and validation Debug and analyze silicon issues with hardware and firmware teams to identify root causes Desired Candidate Profile : Strong hands-on experience in SoC validation and firmware development Experience with SD/MMC protocols and debugging tools Good problem-solving and cross-functional collaboration skills

Job Role Overview: The ideal candidate for this role will be an innovative self-starter. You will be a DDR/LPDDR expert with experience in making architectural trade-offs to optimize DDR/LPDDR performance & power for a variety of use cases. You will collaborate with internal and external development engineers (architecture, hardware, validation, software services). You will be a member of a team analysing the product-level system power & performance for DDR/LPDDR. You will contribute to development, support device characterization, and benchmarking efforts. Job Description : Extensive experience in DDR/LPDDR systems Experience in development, preferably for DDR/LPDDR memory controller. In-depth knowledge and extensive experience with JEDEC specifications for DDR/LPDDR. In-depth knowledge and extensive experience in embedded domain. Requirements: B. Tech in Computer Science, Electrical Engineering. 8+ years of experience in a relevant domain. Strong analytical & abstract thinking ability, along with technical communication skills. Able to work independently and perform in a fast-paced environment. Ability to troubleshoot and debug complex issues. Prior experience in working with Agile/Scrum.

Qualification : Bachelors in Computer Science / Electronics / Electrical Engineering Key Responsibilities: Collaborate with ASIC design teams to ensure DFT rules and coverage are metGenerate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teamsSupport post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-upEnhance and maintain scripting for DFT flows Preferred Experience & Skills:Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG TestKompress MBIST MentorETVerify Simulation VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Location : Bangalore | Hyderabad | Cochin | Pune

code development & debugging for Pre & Post Si Validation Pre & Post Silicon Validation of SoC with Radar based application in automotive & Infotainment domain Zebu or Emulation platform platforms

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with functional tests for silicon validation (e.g., C, C++ or Python) or developing embedded software.. Experience in silicon bring up, functional validation, characterizing, and qualifying silicon.. Experience with board schematics, layout, and debug methodologies using lab equipment.. Preferred qualifications:. Experience in hardware/software integration (i.e. pre-silicon use of emulation and software-based test and diagnostics development).. Experience in scripting languages, such as Python for Automation development.. Experience with Power Characterization, PCIe, DDR.. Experience in RTL design, verification or emulation.. Knowledge of SoC architecture, including boot flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud TPU projects. You will create test plans and test content for exercising the various subsystems in the AI/ML SoC, verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work closely with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.. Responsibilities. Develop and execute tests in post-silicon validation and on HW emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bring up and production.. Ensure validation provides necessary functional coverage for confident design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

MTS/SMTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred ACADEMIC CREDENTIALS: Bachelor s or master s degree in Electronics or Electrical or Computer engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance .