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Senior STA engineer

10 years

0 Lacs

Pune Maharashtra India

Posted:1 week ago| Platform: Linkedin logo

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Skills Required

timing analysis drive constraints design dft analyze reports optimization strategies scripting tcl perl synopsys debugging communication cutting technology

Work Mode

On-site

Job Type

Full Time

Job Description

ACL Digital is looking for a talented and experienced STA (Static Timing Analysis) Engineer to join our growing VLSI team! If you have experience in timing analysis and have worked on full-chip designs , we want to hear from you. Role & Responsibilities: Drive full-chip STA from RTL to GDSII Develop and validate timing constraints (SDC) for complex SoCs Perform timing closure and sign-off using tools like PrimeTime Collaborate with RTL, physical design, and DFT teams for ECOs and timing fixes Analyze timing reports, debug violations, and propose optimization strategies Key Requirements: 5–10 years of hands-on experience in Static Timing Analysis Proven track record in full-chip STA and timing sign-off Strong knowledge of timing constraints, multi-mode/multi-corner (MMMC) flows Familiar with scripting (TCL, Perl) and STA tools (Synopsys PrimeTime preferred) Excellent analytical, debugging, and cross-team communication skills Location: Pune/Bangalore Notice period: Immediate Why ACL Digital? At ACL Digital, you’ll be part of a fast-paced team delivering next-gen semiconductor solutions. We offer opportunities to work on cutting-edge technology with top-tier clients across the globe. Show more Show less

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Palo Alto

201-500 Employees

193 Jobs

    Key People

  • Pankaj Rai

    CEO

  • Chetan Dutta

    Vice President

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