Senior / Lead Verification Engineer

• Job Title

  : Senior / Lead Verification Engineer (8-10 Years) - Sun Silicon Solutions Pvt Ltd

• Experience

  : 8-10 Years

• Employment Type

  : Full-Time

About the Role

• We are a fast-growing semiconductor startup building next-generation ASIC and SoC solutions. We are looking for a Senior / Lead Verification Engineer to own and drive functional verification strategy and execution across complex IPs, subsystems, and full-chip SoCs.
• This role is ideal for experienced verification engineers who have taken designs through verification sign-off and tape-out, can independently build and scale UVM-based environments, and act as a technical leader and mentor while collaborating closely with architecture, RTL, physical design, and post-silicon teams.

Key Responsibilities

Verification Strategy & Ownership

• Define and own end-to-end verification strategy and plans for IPs, subsystems, and SoCs
• Review specifications and architecture documents to identify verification scope, risks, and corner cases
• Drive verification closure and sign-off readiness

UVM Environment Development

• Architect, build, and maintain scalable SystemVerilog/UVM verification environments
• Develop reusable agents, sequences, drivers, monitors, and scoreboards
• Lead development of directed, constrained-random, and scenario-based tests
• Coverage, Debug & Sign-off
• Own functional coverage and code coverage planning, tracking, and closure
• Analyze coverage holes and drive tests to achieve verification completeness
• Lead debug of complex RTL and testbench issues using waveform and log analysis
• Sign off verification readiness for tape-out

Cross-Functional Collaboration

• Work closely with RTL designers to identify root causes and ensure high-quality fixes
• Collaborate with architecture teams to influence design for verifiability
• Support SoC-level integration verification
• Interface with post-silicon and validation teams to correlate pre-silicon vs silicon behavior

Automation & Leadership

• Own regression infrastructure and automation
• Improve simulation efficiency and debug turnaround time
• Review verification deliverables from junior engineers
• Mentor and guide team members on UVM best practices and debug techniques
• Contribute to verification guidelines, checklists, and reusable methodologies

Required Skills

Must-Have Technical Skills

• 8-10 years of hands-on experience in ASIC/SoC functional verification

Strong expertise in:

• o SystemVerilog and UVM
• o Verification planning and execution
• o Functional and code coverage closure

• Deep understanding of:

• o Digital design fundamentals
• o Directed and constrained-random verification

• Extensive experience with simulators:

• o VCS / Xcelium / Questa
• Proven experience with multiple verification sign-offs and tape-outs
• Strong debugging, analytical, and problem-solving skills
• Comfortable working in Linux-based environments

Good to Have

• Experience verifying complex SoC designs
• Strong knowledge of AMBA protocols (AXI, AHB, APB)
• Expertise in Assertion-Based Verification (SVA)
• Experience handling CDC/RDC verification
• Exposure to low-power verification (UPF-aware flows)
• Scripting skills (Python / Perl / Tcl / Shell)
• Experience with FPGA validation or post-silicon bring-up
• Familiarity with formal verification techniques (a plus)

What We Look For

• Strong ownership mindset for verification quality and sign-off
• Ability to independently drive complex verification efforts
• System-level thinking beyond testbench execution
• Clear technical communication and collaboration skills
• Ability to thrive in a fast-paced startup environment
• Passion for improving verification efficiency and robustness

Education

• B.E./B.Tech or M.E./M.Tech in
• Electronics / Electrical / VLSI / Embedded Systems / Related fields

Why Join Us

• Own verification sign-off for real silicon products
• Influence design quality and architecture decisions
• Work across full lifecycle: spec RTL verification tape-out silicon
• Flat organization with access to founders and senior architects
• Competitive compensation + ESOPs

Skills : -

• Senior Lead Verification Engineer ASIC SoC Functional Verification UVM SystemVerilog IP Subsystem Full-Chip SoC Verification Strategy Verification Planning Sign-off Tape-out Scalable UVM Environment Reusable Agents Sequences Drivers Monitors Scoreboards Directed Constrained-Random Scenario-Based Tests Functional Coverage Code Coverage Coverage Closure Debug Waveform Log Analysis RTL Testbench Verification Readiness Cross-Functional Collaboration Architecture Teams RTL Designers SoC Integration Post-Silicon Validation Regression Infrastructure Automation Simulation Efficiency Debug Turnaround Mentoring UVM Best Practices Verification Guidelines Checklists Reusable Methodologies Digital Design Fundamentals Simulators VCS Xcelium Questa AMBA AXI AHB APB Assertion-Based Verification SVA CDC RDC Low-Power Verification UPF Python Perl Tcl Shell FPGA Validation Post-Silicon Bring-up Formal Verification Linux Design Environment Ownership Mindset System-Level Thinking Technical Communication Collaboration Fast-Paced Startup