Senior Lead STA Engineer (Synthesis, LEC, CLP)

5 years

0 Lacs

Posted:5 days ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Company Description

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with a global presence in Silicon Valley, USA, and India, employing over 1300 engineers. The company offers comprehensive engineering solutions that include silicon design, verification, systems, software, and device engineering, AI/ML solutions, and test automation services. With a strong track record of shipping millions of connectivity ICs and achieving first-time right silicon for over 200+ SoC tape-outs, MosChip® is a reliable partner in the semiconductor industry.


Role Description

This full-time role is for a Senior Lead STA Engineer specializing in Synthesis, LEC, and CLP. The role is on-site and located in Hyderabad. Daily responsibilities include performing static timing analysis, developing and implementing design constraints, synthesis and timing closure for complex designs, working on logic equivalence checking, and collaborating with cross-functional teams to ensure efficient design implementation and verification processes.


Qualifications

  • Expertise in Static Timing Analysis (STA), Synthesis, LEC (Logical Equivalence Checking), and CLP (Clock Power Reduction)
  • Experience with EDA tools such as Synopsys PrimeTime, CADENCE Tempus
  • Proficiency in scripting languages like Perl, TCL, and Shell
  • Strong understanding of digital design fundamentals and VLSI design flow
  • Experience with backend design processes including Physical Design and Signoff flows
  • Excellent communication and teamwork skills
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • Over 5+ years of relevant industry experience is preferred

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