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Smart Soc Solutions
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RTL & Synthesis combined skills

RTL & Synthesis combined skills

Smart Soc Solutions

5 - 8 years

4 - 7 Lacs

Hyderabad

Posted:22 hours ago| Platform:

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Skills Required

ip drg rtl design rtl coding rtl verilog c++ soc electrical engineering digital design vhdl axi fpga perl system verilog arm synthesis asic sta asic verification cdc c ip technical management uvm asic design rdc lint ethernet dft fpga design vlsi

Work Mode

Work from Office

Job Type

Full Time

Job Description

Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech)

Excellent communication skills, both verbal and written

Experience:

5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design

Strong understanding of digital basics

Proficiency in RTL coding (Verilog), IP design, and RTL integration

Hands-on experience with LINT, CDC, and RDC

Experience in writing UPFs and CLP/VCLP checks

Familiarity with synthesis flow and validating design constraints

Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc.

Strong scripting knowledge

Responsibilities:

Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams

Ability to take on the role of a Technical Manager while maintaining hands-on contributions

NoteInterested candidates should provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering)
Job Location IndiaBangalore IndiaHyderabad

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RTL & Synthesis combined skills